UPD780862MCA2-XXX-5A4 データシートの表示（PDF） - NEC => Renesas Technology
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UPD780862MCA2-XXX-5A4 Datasheet PDF : 415 Pages
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CHAPTER 1 GENERAL
Table 1-2. Functional Outline of µPD78054Y Subseries (1/2)
Part Number
Item µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y µPD78P058Y
Internal ROM
memory
Mask ROM
16K bytes
24K bytes 32K bytes
40K bytes
48K bytes
60K bytes
PROM
60K bytesNote 1
High-speed RAM 512 bytes 1024 bytes
1024 bytesNote 1
Buffer RAM
32 bytes
Expansion RAM None
1024 bytes 1024 bytesNote 2
Memory space
64K bytes
General-purpose register 8 bits × 8 × 4 banks
Minimum With main
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz)
instruction system clock
execution With subsystem 122 µs (at 32.768 kHz)
time
clock
Instruction set
• 16-bit operation
• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjustment, etc.
I/O port
• Total
: 69
• CMOS input
:2
• CMOS I/O
: 63
• N-ch open-drain I/O : 4
A/D converter
8-bit resolution × 8 channels
D/A converter
Serial interface
8-bit resolution × 2 channels
• 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable
: 1 channel
• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel
• 3-wire serial I/O/UART mode selectable
: 1 channel
Timer
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
Timer output
3 (14-bit PWM output: 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with
main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)
Notes 1. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory
size select register (IMS).
2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select
register (IXS).
8
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