AD9288BSTZ-100 データシートの表示（PDF） - Analog Devices

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AD9288BSTZ-100

8-Bit, 40/80/100 MSPS Dual A/D Converter

Analog Devices 

TIMING DIAGRAMS

AD9288

SAMPLE N

SAMPLE N + 1

SAMPLE N + 5

AINA, AINB

tA

ENCODE A, B

tEH

tEL

SAMPLE N + 2 SAMPLE N + 3 SAMPLE N + 4

1/fs

D7A–D0A

DATA N – 4

DATA N – 3

DATA N – 2

tPD

DATA N – 1

DATA N

tV

DATA N + 1

D7B–D0B

DATA N – 4

DATA N – 3

DATA N – 2

DATA N – 1

DATA N

Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing

DATA N + 1

SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE

N

N+1

N+2

N+3

N+4

AINA, AINB

tA

tEH

tEL

ENCODE A

1/fs

ENCODE B

tPD

tV

D7A–D0A

D7B–D0B

DATA N – 8

DATA N – 6

DATA N – 4

DATA N – 2

DATA N

DATA N + 2

DATA N – 7

DATA N – 5

DATA N – 3

DATA N – 1

DATA N + 1 DATA N + 3

Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing

Rev. C | Page 5 of 24

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