H8S/2116 データシートの表示（PDF） - Renesas Electronics
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H8S/2116 Datasheet PDF : 842 Pages
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2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................ 49
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) .................................. 49
2.7.8 Memory Indirect—@@aa:8 ............................................................................... 50
2.7.9 Effective Address Calculation ............................................................................ 51
2.8 Processing States ................................................................................................................ 53
2.9 Usage Notes ........................................................................................................................ 55
2.9.1 Note on TAS Instruction Usage.......................................................................... 55
2.9.2 Note on STM/LDM Instruction Usage ............................................................... 55
2.9.3 Note on Bit Manipulation Instructions................................................................ 55
2.9.4 EEPMOV Instruction.......................................................................................... 56
Section 3 MCU Operating Modes ....................................................................... 57
3.1 Operating Mode Selection .................................................................................................. 57
3.2 Register Descriptions.......................................................................................................... 58
3.2.1 Mode Control Register (MDCR) ........................................................................ 58
3.2.2 System Control Register (SYSCR)..................................................................... 59
3.2.3 Serial Timer Control Register (STCR) ............................................................... 61
3.2.4 System Control Register 3 (SYSCR3) ................................................................ 63
3.3 Operating Mode Descriptions ............................................................................................. 63
3.3.1 Mode 2................................................................................................................ 63
3.4 Address Map....................................................................................................................... 64
Section 4 Exception Handling ............................................................................. 65
4.1 Exception Handling Types and Priority.............................................................................. 65
4.2 Exception Sources and Exception Vector Table................................................................. 66
4.3 Reset ................................................................................................................................... 69
4.3.1 Reset Exception Handling .................................................................................. 69
4.3.2 Interrupts Immediately after Reset...................................................................... 70
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ....................................... 70
4.4 Interrupt Exception Handling ............................................................................................. 71
4.5 Trap Instruction Exception Handling.................................................................................. 71
4.6 Stack Status after Exception Handling ............................................................................... 72
4.7 Usage Note ......................................................................................................................... 73
Section 5 Interrupt Controller.............................................................................. 75
5.1 Features............................................................................................................................... 75
5.2 Input/Output Pins................................................................................................................ 77
5.3 Register Descriptions.......................................................................................................... 78
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD).......................................... 78
5.3.2 Address Break Control Register (ABRKCR) ..................................................... 80
Rev. 1.00 Mar. 02, 2006 Page x of xl
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