R8830 データシートの表示（PDF） - RDC Semiconductor
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R8830 Datasheet PDF : 97 Pages
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RDC®
RISC DSP Controller
R8830
13. Chip Select Unit
The Chip Select Unit provides 12 programmable chip select pins to access a specific memory or peripheral device.
The chip selects are programmed through five peripheral control registers (A0h, A2h, A4h, A6h, A8h). And all of the
chip selects can be insert wait states by programmed the peripheral control register.
13.1 UCS
The UCS default to active on reset for program code access. The memory active range is upper 512k (80000h – FFFFFh),
which is programmable. And the default memory active range of UCS is 64k ( F0000h – FFFFFh).
The UCS active to drive low four CLKOUTA oscillators if no wait state inserts. There are three wait-states insert to UCS
active cycle on reset.
Upper Memory Chip Select Register
Offset : A0h
Reset Value :F03Bh
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
1
LB2 - LB0
0
0
0
0 DA 0
1
1
1 R2 R1 R0
Bit 15 : Reserved
Bit 14-12 : LB2-LB0, Memory block size selection for UCS chip select pin.
The UCS chip select pin active region can be configured by the LB2-LB0.
The default memory block size is from F0000h to FFFFFh.
LB2, LB1, LB0 ---- Memory Block size , Start address, End Address
1 , 1 , 1 ---- 64k
, F0000h , FFFFFh
1 , 1 , 0 ---- 128k
, E0000h , FFFFFh
1 , 0 , 0 ---- 256k
, C0000h , FFFFFh
0 , 0 , 0 ---- 512k
, 80000h , FFFFFh
Bit 11-8 : Reserved
Bit 7 : DA , Disable Address. If the BHE / ADEN pin is held high on the rising edge of RST , then the DA bit is valid to
enable/disable the address phase of the AD bus. If the BHE / ADEN pin is held high on the rising edge of RST , the
AD bus always drive the address and data.
Set 1 : Disable the address phase of the AD15 – AD0 bus cycle when UCS is asserted.
Set 0 : Enable the address phase of the AD15 – AD0 bus cycle when UCS is asserted.
Bit 6-3: Reserved
Bit 2 : R2, Ready Mode. This bit is used to configure the ready mode for UCS chip select.
Set 1: external ready is ignored.
Set 0: external ready is required.
Bit 1-0 : R1-R0, Wait-State value. When R2 is set to 0, it can inserted wait-state into an access to the UCS memory area.
RDC Semiconductor Co.
Subject to change without notice
31
Rev:1.4
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