RFRXD0420 データシートの表示（PDF） - Microchip Technology

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RFRXD0420

UHF ASK/FSK/FM Receiver

Microchip Technology 

rfRXD0420/0920

Approximate LNA noise figures are listed in Table 2-3.

TABLE 2-3: LNA NOISE FIGURES

Device

Noise Figure(1)

rfRXD0420

TBD

rfRXD0920

TBD

Note 1: Approximate value

LNAIN (Pin 31) has an input impedance of approxi-

mately 26 Ω || 2 pF single-ended.

LNAOUT (Pin 3) has an open-collector output and is

pulled up to VDD via a tuned circuit.

Important: To ensure LNA stability the VSS pin (Pin 1)

must be connected to a low impedance ground.

The LNA pins are illustrated in Figure 2-3.

FIGURE 2-3: BLOCK DIAGRAM OF LNA

PINS

VDD

LNAIN

31

1.6V

0.8V

5 kΩ

VSS

LNAOUT

3

VSS

VDD

VSS

1

VSS

The gain of the LNA can be selected between High and

Low Gain modes by the LNAGAIN pin (Pin 2). LNAGAIN

is a CMOS input with hysteresis. Table 2-4 summarizes

the voltage levels and modes for LNA gain.

In the High Gain mode the LNA operates normally. In

Low Gain mode the gain of the LNA is reduced approx-

imately 25 dB, reduces total supply current, and

increases maximum input signal levels (see Electrical

Characteristics section for values).

TABLE 2-4: LNA GAIN CONTROL

LNAGAIN

< 0.8 V

> 1.4 V

Description

High Gain mode

Low Gain mode

2.4 MIXER1 and IF Preamp

MIXER1 performs down-conversion of the RF signal to

the Intermediate Frequency (IF) and is followed by an

IF preamplifier.

1IFIN (Pin 4) has an approximately 33 Ω single-ended

input impedance. The 1IFIN pin is illustrated in Figure 2-

4.

The 1IF+ (Pin 6) and 1IF- (Pin 7) are bias connections

to the MIXER1 balanced collectors. Both pins are

open-collector outputs and are individually pulled up to

VDD by a load resistor. The MIXER1 bias pins are illus-

trated in Figure 2-5.

1IFOUT (Pin 9) has an approximately 330 Ω single-

ended output impedance. The 330 Ω impedance

provides a direct match to low cost ceramic IF filters.

The 1IFOUT pins is illustrated in Figure 2-6.

FIGURE 2-4: BLOCK DIAGRAM OF MIXER1

PIN

VDD

1IFIN

4

VSS

13 Ω

13 Ω

500 µA

VSS

FIGURE 2-5: BLOCK DIAGRAM OF MIXER1

BIAS PINS

1IF+

6

VDD

20 pF

VSS

500 µA

VSS

VDD

20 pF

1IF-

7

VSS

500 µA

VSS

FIGURE 2-6: BLOCK DIAGRAM OF IF

PREAMP PIN

VDD

1IFOUT

9

130 Ω

VDD

VDD

6.8 kΩ

230 µA

VSS

VSS

2.5 IF Limiting Amplifier with RSSI

The IF Limiting Amplifier amplifies and limits the IF

signal at the 2IFIN pin (Pin 11). It also generates the

Received Signal Strength Indicator (RSSI) signal

(Pin 21).

2.5.1 IF LIMITING AMPLIFIER

Magnitude control circuitry is used in the last stage of

the receiver to keep the signal constant for demodula-

tion. It can consist of a limiting or Automatic Gain

Control (AGC) amplifier. A limiting amplifier is

DS70090A-page 6

Preliminary

 2003 Microchip Technology Inc.

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