Q67121-C1007 データシートの表示（PDF） - Siemens AG

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Q67121-C1007

16-Bit CMOS Single-Chip Microcontroller

Siemens AG 

1996 Intermediate Version

C161

General Purpose Timer (GPT) Units

The GPT units represent a very flexible multifunctional timer/counter structure which may be used

for many different time related tasks such as event timing and counting, pulse width and duty cycle

measurements, pulse generation, or pulse multiplication.

Two separate modules, GPT1 and GPT2, are available (GPT2 on C161O only). Each timer in each

module may operate independently in a number of different modes, or may be concatenated with

another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three

basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the

input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while

Counter Mode allows a timer to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of

a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has

one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the

timers in module GPT1 is 500 ns (@ 16-MHz CPU clock).

The count direction (up/down) for each timer is programmable by software or may additionally be

altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.

Figure 5

Block Diagram of GPT1

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/

underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for time out monitoring

of external hardware components, or may be used internally to clock timers T2 and T4 for

measuring long time periods with high resolution.

Semiconductor Group

16

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