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SAF7115HW データシートの表示(PDF) - NXP Semiconductors.

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SAF7115HW Datasheet PDF : 35 Pages
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NXP Semiconductors
SAF7115
Multistandard video decoder
Table 4. Pin description …continued
Symbol
Pin
Type[1]
Description
HTQFP100 TFBGA160
Supplies (digital)
VDDD(IO)
1, 25, 51 and A1, A14, P1 P
75
and P14
I/O digital supply voltage
VDDD(CORE)
33, 43, 58, B5, B10,
P
68, 83 and 93 E13, K13, N5
and N10
core digital supply voltage
VSSD(CORE) 38, 63 and 88 A8, H14 and P
P7
core digital ground supply voltage
VSSD(IO)
26, 50, 76
and 100
D4 to D11, P
E4 to E11,
F4 to F11,
G4 to G11,
H4 to H11,
J4 to J11,
K4 to K11
and L6 to L9
I/O digital ground supply voltage
Analog inputs
AGND
21
L2
P
analog signal ground reference for all AIx inputs
AI21
16
J1
AI
analog input 21
AI22
14
H1
AI
analog input 22
AI23
12
G1
AI
analog input 23
AI24
10
F2
AI
analog input 24
AI2D
13
G2
AI
differential input for ADC channel 2 (pins AI24, AI23, AI22 and
AI21)[5]
AI11
20
L1
AI
analog input 11
AI12
18
K1
AI
analog input 12
AI1D
19
K2
AI
differential input for ADC channel 1 (pins AI12 and AI11)[5]
Analog output
AOUT
22
M1
AO
analog test output (do not connect)
I2C-bus
SCL
31
N4
I (/O)/od serial clock input (/output) with inactive output path
SDA
32
P4
I (/O)/od serial data input (/output)
General control
CE
27
N2
I/pu
chip enable or reset input (with internal pull-up)
RESO_N 30
P3
O
reset output (active low)
Audio clock
ALRCLK 40
P8
(I/) O/st/pd audio left/right clock output: can be strapped to supply through a
3.3 kresistor indicating that the default 24.576 MHz crystal
(internal pull-down) has been replaced by a 32.11 MHz crystal
AMCLK
37
N7
O
audio master clock output
AMXCLK 41
N9
I
audio master external clock input
ASCLK
39
N8
O
audio serial clock output
SAF7115_1
Product data sheet
Rev. 01 — 15 October 2008
© NXP B.V. 2008. All rights reserved.
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