MU9C1480A データシートの表示（PDF） - Music Semiconductors
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MU9C1480A Datasheet PDF : 28 Pages
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MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
Address register must contain a unique value to prevent
bus contention. This process allows individual device
selection. The Page Address register initialization works
as follows: Writes to Page Address registers are only active
for devices with /FI LOW and /FF HIGH. At initialization,
all devices are empty, thus the top device in the string will
respond to a TCO PA instruction, and load its PA register.
To advance to the next device in the string, a Set Full Flag
(SFF) instruction is used, which is active only for the device
with /FI LOW and /FF HIGH. The SFF instruction changes
the first device’s /FF to LOW, although the device really is
empty, which allows the next device in the string to respond
to the TCO PA instruction and load its PA register. The
initialization proceeds through the chain in a similar manner
filling all the PA registers in turn. Each device must have a
unique Page Address value stored in its PA register, or
contention will result. After all the PA registers are filled,
the entire string is reset through the Control register, which
does not change the values stored in the individual PA
registers. After the reset, the Device Select registers usually
are set to FFFFH to enable operation in Case 1 of Table 5a
on page 12. The Control registers and the Segment Control
registers are then set to their normal operating values for
the application.
Vertically Cascaded System Initialization
Table 6 shows an example of code that initializes a
daisy-chained string of LANCAM devices. The
initialization example shows how to set the Page Address
registers of each of the devices in the chain through the
use of the Set Full Flag instruction, and how the Control
registers and Segment counters of all the LANCAM devices
are set for a typical application. Each Page Address register
must contain a unique value (not FFFFH) to prevent bus
contention.
For typical daisy chain operation, data is loaded into the
Comparand registers of all the devices in a string
simultaneously by setting DS=FFFFH. Since reading is
prohibited when DS=FFFFH (except for the device with a
match), for a diagnostic operation you need to select a
specific device by setting DS=PA for the desired device to
be able to read from it. Refer to Tables 5a and 5b on page 12
for preconditions for reading and writing.
Initialization for a single LANCAM is similar. The Device
Select register in this case is usually set to equal the Page
Address register for normal operations. Also, the dedicated
/MA flag output can be used instead of /MF, allowing /EC
to be tied HIGH.
Cycle Type
Op-Code
Control bus
Comments
on DQ Bus /E /CM /W /EC
Command read
L
LH
H Clear power-up anomalies.
Command write TCO DS
L
L
L
H Target Device Select register to disable local device selection.
Command write FFFFH
L
L
L
H Disable Device Select feature.
Commandwrite TCO CT
L
L
L
H Target Control register for reset.
Command write 0000H
L
L
L
H Causes Reset.
Command write TCO PA
L
L
L
H Target Page Address register to set page for cascaded operation.
Command write
Command write
nnnnH
SFF
L
L
L
L
L
L
H Page Address value.
H Set Full flag; allows access to next device (repeat previous
two cycles plus this one for each device in chain.
Command write TCO CT
L
L
L
Commandwrite 0000H
L
L
L
Command write TCO CT
L
L
L
Command write 8040H
L
L
L
Command write TCO SC
L
L
L
Command write 3808H
L
L
L
H Target Control register for reset of Full flags, but not Page address.
H Causes Reset.
H Target Control register for initial values.
H Control register value.
H Target Segment Count Control register
H Set both Segment counters to write to Segment 1, 2, and 3, and
read from Segment 0.
Command write SPS M@HM L L L
H Set Data reads from Segment 0 of the Highest-Priority match.
Notes
1
2
2
2,3
1
1
4
4
4
Notes:
1. Toggling the /RESET pin generates the same effect as this reset of the Control register, but good programming
practice dictates a software reset for initialization to account for all possible prior conditions.
2. This instruction may be omitted for a single LANCAM application.
3. The last SFF will cause the /FF pin in the last chip in a daisy chain to go LOW. In a daisy chain, DS needs to be set equal to PA
to read out a particular chip prior to a match condition.
4. A typical LANCAM control environment: Enable match flag; Enable full flag; 48 CAM bits, 16 RAM bits; Disable comparison
masking; and Enable address increment. See Table 8 on page 21 for Control Register bit assignments.
Table 6: Example Initialization Routine
Rev. 3.0 Draft
16
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