ST802RT1B データシートの表示（PDF） - STMicroelectronics

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ST802RT1B

10/100 real-time Ethernet 3.3 V transceiver

STMicroelectronics 

ST802RT1A, ST802RT1B

Pin description

Table 4.

Pin n°

Pin functions of the ST802RT1x

Name

Type

Function

Data interface

5

TXD0

Transmit data. The media access controller (MAC) drives data to the

ST802RT1x using these inputs.

6

TXD1

I txd0 = MII/RMII tx data

7

TXD2

txd1 = MII/RMII tx data

8

TXD3

txd2/txd3 = MII tx data

7

SCLK

I RMII clock (50 Mhz)

2

TX_EN

I, PD

MII transmit enable. The MAC asserts this signal when it drives valid data on

the txd inputs.

MII transmit clock. Normally the ST802RT1x drives tx_clk.

1

TX_CLK O, PD 25 MHz for 100 Mbps operation

2.5 MHz for 10 Mbps operation

40

RXER

O

Receive error. The ST802RT1x asserts this output when it receives invalid

symbols from the network.

42

RXD3

Receive data. The ST802RT1x drives received data on these outputs.

43

RXD2

rxd0 = MII/RMII rx data

O, PD

44

RXD1

rxd1 = MII/RMII rx data

45

RXD0

rxd2/rxd3 = MII rx data

38

RXDV /

CRSDV

O, PD

Receive data valid. (MII = RXDV, RMII = CRSDV). The ST802RT1x asserts

this signal when it drives valid data on rxd.

MII receive clock. This continuous clock provides reference for rxd, rx_dv, and

rx_er signals.

37

RX_CLK

O 25 MHz for 100 Mbps operation.

2.5 MHz for 10 Mbps operation.

MII collision detection. The ST802RT1x asserts this output when detecting a

46

COL

O collision. This output remains high for the duration of the collision. This signal is

asynchronous and inactive during full-duplex operation.

MII carrier sense. During half-duplex operation (RN00[8]=0), the ST802RT1x

39

CRS

O

asserts this output when either transmit or receive medium is non idle. During

full-duplex operation (RN00[8]=1), crs is asserted only when the receive

medium is non-idle.

MII control interface

31

MDC

Management data clock. Clock for the MDIO serial data channel. One MDC

I transition is also required to complete a device reset.

Maximum frequency is 2.5 MHz.

30

MDIO

I/O, PU

Management data input/output. Bi-directional serial data channel for PHY

communication.

9

MDINT

OD Management data interrupt.

Physical (twisted pair) interface

35

X1

Xtal in (25 Mhz). 25 MHz reference clock input. When an external 25 MHz

I crystal is used, this pin must be connected to one of its terminals. If an external

25 MHz oscillator clock source is used, then this pin will be its input pin.

Doc ID 17049 Rev 1

13/58

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