SX1781 データシートの表示（PDF） - Semtech Corporation
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SX1781 Datasheet PDF : 16 Pages
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SX1781
PLL Frequency Synthesizer with integrated VCO
ADVANCED COMMUNICATIONS & SENSING
FINAL
DATASHEET
7. Input Reference Signal
The input reference signal of the PLL enters pin 2 CLK. To meet the phase noise performance of the synthesizer, the phase
noise of the clock source (denoted PNCLK) at a 10 kHz distance of the carrier should be such that:
PNCLK < -160 + 20.log(Rdiv+1) dBc/Hz @ 10 kHz
A TCXO is an appropriate signal source at CLK input.
Two different connection schemes are possible, depending of the type of source :
CMOS output device : the source should be directly DC connected to the CLK input, and its levels should be compliant
with the specification of Table 6.
Sine or clipped sine output: AC coupling, through a 560pF capacitor, should be used. In this case a minimum swing of
0.5 volts triggers the divider input (see Table 6).
8. RF Frequency Setting
The RF Output frequency is calculated from the following formula:
Fout
=
Fref
Rdiv +
1
*
Ndiv
+
2
4800
Where
Ndiv is controlled in a 10-bit register and Rdiv in a 6-bit register to be programmed through the SPI interface.
Fref is the input reference frequency, of the signal applied on pin 2 (CLK). Note that the recommended value of
Fref
Rdiv +1 is 500 kHz, which allows for a minimum frequency step of 250 kHz.
9. Lock Detector and Squelch
A lock detection signal is mapped to pin 16 LD. It can be used as an interrupt request signal to the external world. This
signal can also be used to internally shut down the output buffers until the PLL gets locked. This squelch function can be
inhibited by setting bit 3 at address 3 to “1” (default = “0”, squelch active).
Rev 1 - November 2008
©2008 Semtech Corp.
Page 9
www.semtech.com
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