PHC21025 データシートの表示（PDF） - Philips Electronics
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PHC21025 Datasheet PDF : 16 Pages
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Philips Semiconductors
Complementary enhancement
mode MOS transistors
Product specification
PHC21025
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
Per channel
VDS
drain-source voltage (DC)
N-channel
P-channel
VGSO
ID
gate-source voltage (DC)
drain current (DC)
N-channel
P-channel
IDM
peak drain current
N-channel
P-channel
Ptot
total power dissipation
Tstg
storage temperature
Tj
operating junction temperature
Source-drain diode
IS
source current (DC)
N-channel
P-channel
ISM
peak pulsed source current
N-channel
P-channel
open drain
Ts ≤ 80 °C
note 1
Ts = 80 °C; note 2
Tamb = 25 °C; note 3
Tamb = 25 °C; note 4
Tamb = 25 °C; note 5
Ts ≤ 80 °C
note 1
−
30
V
−
−30
V
−
±20
V
−
3.5
A
−
−2.3
A
−
14
A
−
−10
A
−
2
W
−
2
W
−
1
W
−
1.3
W
−65
+150 °C
−
150
°C
−
1.5
A
−
−1.25 A
−
6
A
−
−5
A
Notes
1. Pulse width and duty cycle limited by maximum junction temperature.
2. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 2 W at the same time.
3. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp
(ambient to tie-point) of 27.5 K/W.
4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp
(ambient to tie-point) of 90 K/W.
5. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with
an Rth a-tp (ambient to tie-point) of 90 K/W.
1997 Jun 20
3
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