UBA20272T データシートの表示（PDF） - NXP Semiconductors.

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UBA20272T

350 V and 600 V Power ICs for dimmable compact fluorescent lamps

NXP Semiconductors. 

NXP Semiconductors

UBA20271/2

350 V and 600 V Power ICs for dimmable compact fluorescent lamps

When CP is lower than Vth(rel)CP, the IC is released from the hold state and moves to the

start-up state. See Figure 3. Alternatively, the hold state ends when the supply voltage is

lower than VDD(rst) and the IC is reset.

With a 470 nF capacitor on the CP pin, the typical hold state retention delay is between

1.0 seconds and 1.7 seconds. However, it depends on where the preheat cycle is cut off

on the rising or falling edge of the preheat timing. The retention time for a failed ignition

always starts from the top of the rising edge on the CP pin. See Figure 5. In the hold state,

a latch is set (hold state latch = 1), the oscillator is stopped, transistor HS is

non-conductive and transistor LS conducting. The voltage on pin VDD alternates between

VDD(start) and VDD(stop) as long as the voltage on the CP pin has not reached Vth(rel)CP. See

Figure 5.

The alternating supply voltage is a result of the current drawn by the IC supply pin VDD.

The supply current is less than 220 A, when the supply voltage VDD is increasing

between VDD(stop) and VDD(start). The supply current is typically 2 mA when VDD is

decreasing between VDD(start) and VDD(stop). More current is drawn during the decreasing

slope of VDD as the internal analog supply is turned on when VDD > VDD(start). This

condition enables comparators in the IC to monitor the voltage on the CP pin and whether

the supply voltage VDD decreases lower than VDD(stop).

7.2 Oscillation and timing

7.2.1 Oscillation

The internal oscillator is a VCO circuit which generates a sawtooth waveform between the

Vth(CF)max level and 0 V. Capacitor CCF, resistor Rext(RREF), and the voltage at the CI pin

determine the frequency of the sawtooth. Rext(RREF) and CCF determine the minimum and

maximum switching frequencies. Their ratio is internally fixed. There are two ratios, the

ratio between fbridge(max) and fbridge(min) is 2.5 and the ratio between fbridge(max) and

fbridge(bst)min is 4.6. The sawtooth frequency is twice the half-bridge frequency.

Transistors HS (Q1) and LS (Q2) are brought into conduction with a duty cycle of

approximately 50 %. Figure 8 provides an overview of the oscillator signal and driver

signals. The oscillator starts oscillating at fbridge(max). The non-overlap time between the

gate drive signals VGLS and VGHS is tno.

UBA20271_UBA20272

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2.1 — 12 October 2011

© NXP B.V. 2011. All rights reserved.

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