X4003 データシートの表示（PDF） - Xicor -> Intersil

部品番号

コンポーネント説明

メーカー

X4003

CPU Supervisor

Xicor -> Intersil 

X4003/X4005

TIMING DIAGRAMS

Bus Timing

tF

tHIGH

SCL

SDA IN

tSU:STA

tHD:STA

tSU:DAT

tLOW

tHD:DAT

SDA OUT

tR

tA

tDH

WP Pin Timing

SCL

SDA IN

WP

Start

Clk 1

Slave Address Byte

Clk 9

tSU:WP

tHD:WP

tSU:STO

tBUF

Write Cycle Timing

SCL

SDA

8th Bit of Last Byte

ACK

tWC

Stop

Condition

Start

Condition

Nonvolatile Write Cycle Timing

Symbol

tWC(7)

Parameter

Write cycle time

Min.

Typ.(1)

5

Max.

10

Unit

ms

Note: (7) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.

It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

REV 1.1.3 4/30/02

www.xicor.com

Characteristics subject to change without notice. 12 of 18

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