UJA1076TW/3V3 データシートの表示（PDF） - NXP Semiconductors.

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UJA1076TW/3V3

High-speed CAN core system basis chip

NXP Semiconductors. 

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

6.2 SPI

6.2.1 Introduction

The Serial Peripheral Interface (SPI) provides the communication link with the

microcontroller, supporting multi-slave operations. The SPI is configured for full duplex

data transfer, so status information is returned when new control data is shifted in. The

interface also offers a read-only access option, allowing registers to be read back by the

application without changing the register content.

The SPI uses four interface signals for synchronization and data transfer:

• SCSN: SPI chip select; active LOW

• SCK: SPI clock; default level is LOW due to low-power concept

• SDI: SPI data input

• SDO: SPI data output; floating when pin SCSN is HIGH

Bit sampling is performed on the falling clock edge and data is shifted on the rising clock

edge (see Figure 4).

SCS

SCK

01

02

03

04

sampled

15

16

SDI

X

MSB

14

13

12

01

LSB

X

SDO

X

MSB

14

13

12

floating

Fig 4. SPI timing protocol

01

LSB

floating

mce634

6.2.2 Register map

The first three bits (A2, A1 and A0) of the message header define the register address.

The fourth bit (RO) defines the selected register as read/write or read only.

Table 3. Register map

Address bits 15, 14 and 13

000

001

010

011

Write access bit 12 = 0

0 = read/write, 1 = read only

0 = read/write, 1 = read only

0 = read/write, 1 = read only

0 = read/write, 1 = read only

Read/Write access bits 11... 0

WD_and_Status register

Mode_Control register

Int_Control register

Int_Status register

UJA1076_2

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 02 — 27 May 2010

© NXP B.V. 2010. All rights reserved.

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