UPD16835AGS-BGG データシートの表示（PDF） - NEC => Renesas Technology
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UPD16835AGS-BGG Datasheet PDF : 32 Pages
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µPD16835A
Table 5-6. 7th Byte Data Configuration (Initial data)
Bit
D7
D6
D5
D4
D3
Data
0 or 1 0 or 1 0 or 1 0 or 1 0 or 1
Remark Bits D4 to D7 : Reference voltage 2 (EVR β2)
Bits D0 to D3 : Reference voltage 1 (EVR β1)
D2
0 or 1
D1
0 or 1
D0
0 or 1
<8th byte>
The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H.
If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the
checksum output pin (EXT pin) is kept “L”.
(2) Standard data input
<1st byte>
The 1st byte specifies the type of data and whether the EXP pin output is used, such as when the initial data is
input.
Table 5-7. 1st Byte Data Configuration
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Data
1
1
1
0
0 or 1 0 or 1 0 or 1 0 or 1
The EXP pin goes low (current sink) when the input data is “0”, and high (high impedance state) when the input
data is “1”. Input “0” to bit D4.
<2nd byte>
The 2nd byte specifies the rotation direction of the α channel, enables output of the α channel, and the number of
pulses (252 pulses MAX.) during the 1VD period (in 1 cycle of FF2) of the α channel.
Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is
“0”; it is in the reverse direction (CCW mode) when the bit is “1”.
Bit D6 is used to enable the output of the α channel. The α channel enters the high impedance state when this bit
is “0”; it is in conduction mode when the bit is “1”.
The number of pulses is set by bits D0 to D5. It is set by 6 bits in terms of software. However, the actual circuit
uses an 8-bit counter with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually
generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x 4. The number of
pulses can be set to a value in the range of 0 to 252, in units of 4 pulses.
16
Data Sheet S15973EJ1V0DS
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