UPD16835AGS-BGG データシートの表示（PDF） - NEC => Renesas Technology

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UPD16835AGS-BGG

MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT

NEC => Renesas Technology 

µPD16835A

5. INTERFACE (I/F) CIRCUIT DATA CONFIGURATION (fCLK = 4-MHz EXTERNAL CLOCK INPUT)

Input data consists of serial data (8 bytes x 8 bits).

Input serial data with the LSB first, from the 1st byte to 8th byte.

(1) Initial data

<1st byte>

Bit

Data

Function

Setting

D7 1

HEADER DATA2 DATA selection

D6 1

HEADER DATA1

D5 1

HEADER DATA0

D4 0

−

−

D3 1 or 0

EXP3

Hi-Z or L

D2 1 or 0

EXP2

Hi-Z or L

D1 1 or 0

EXP1

Hi-Z or L

D0 1 or 0

EXP0

Hi-Z or L

Remark Hi-Z : High impedance,

L : Low level (current sink)

(2) Standard data

<1st byte>

Bit

Data

Function

D7

0

HEADER DATA2

D6

0

HEADER DATA1

D5

0

HEADER DATA0

D4

0

−

D3

1 or 0

EXP3

D2

1 or 0

EXP2

D1

1 or 0

EXP1

D0

1 or 0

EXP0

Remark Hi-Z : High impedance,

L : Low level (current sink)

Setting

DATA selection

−

Hi-Z or L

Hi-Z or L

Hi-Z or L

Hi-Z or L

<2nd byte>

Bit

Data

Function

D7

D6

D5

D4 8-bit data

First Point Wait

D3

input Note

D2

D1

D0

Note Input other than “0”.

Setting

Start point wait

256 µs to 65.28 ms

Setting

(1 to 255)

∆t = 256 µs

<2nd byte>

Bit

Data

Function

Setting

D7

1 or 0

α ROTATION α ch CCW/CW

D6

1 or 0

α ENABLE

α ch ON/OFF

D5

α ch

D4

D3

6-bit data

Number of

D2

input

α Pulse Number

pulses in 1 VD

Setting (0 to 63)

D1

∆n = 4 pulses Note

D0

Note The number of pulses can be varied in 4-pulse

steps.

<3rd byte>

Bit

Data

Function

Setting

D7

D6

Start point drive

D5

wait

D4 8-bit data First Point

256 µs to 65.28 ms

D3

input Note

Magnetize Wait Setting

D2

(1 to 255)

D1

∆t = 256 µs

D0

Note Input other than “0”.

<3rd byte>

Bit

Data

D7

15-bit data

D6

D5

D4

D3

Low-order

D2

8-bit data

D1

input

D0

Function

α Pulse Width

Setting

α ch pulse

cycle

0.25 to 8191.75 µs

Setting

(1 to 32767)

∆t = 0.25 µs

Data Sheet S15973EJ1V0DS

9

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