UPD178P018A データシートの表示（PDF） - NEC => Renesas Technology

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UPD178P018A

8-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

µPD178P018A

PLL frequency

synthesizer

Item

Division mode

Reference frequency

Charge pump

Phase comparator

Frequency counter

D/A converter (PWM output)

Standby function

Reset

Power supply voltage

Package

(2/2)

Function

Two types

• Direct division mode (VCOL pin)

• Pulse swallow mode (VCOH and VCOL pins)

7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz)

Error out output: 2 (EO0 and EO1 pins Note 1)

Unlock detectable by program

• Frequency measurement

• AMIFC pin: for 450-kHz count

• FMIFC pin: for 450-kHz/10.7-MHz count

8-/9-bit resolution × 3 channels (shared by 8-bit timer)

• HALT mode

• STOP mode

• Reset via the RESET pin

• Internal reset by watchdog timer

• Reset by power-ON clear circuit (3-value detection)

• Detection of less than 4.5 V Note 2 (CPU clock: fX)

• Detection of less than 3.5 V Note 2 (CPU clock: fX/2 or less and on power application)

• Detection of less than 2.5 V Note 2 (in STOP mode)

• VDD = 4.5 to 5.5 V (with PLL operating)

• VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less)

• VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX)

• 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)

• 80-pin ceramic WQFN (14 × 14 mm, 0.65-mm pitch)

Notes 1. The EO1 pin can be set to high impedance for the µPD178P018A.

The following figure shows an application example.

µ PD178P018A

EO0

EO1

VCOH

VCOL

LPF VCO To Mixer

LPF : Low path filter

VCO : Voltage controlled oscillator

• To lock to a target frequency at high speed

Setting the EO0 and EO1 pins to error out output improves the output current potential and LPF

voltage control potential.

• Normal state

Setting only the EO0 pin to error out output maintains the LPF stable.

2. These voltage values are maximum values. Reset is actually executed at a voltage lower than these

values.

4

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