V62C1801024L-70T データシートの表示（PDF） - Mosel Vitelic Corporation

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V62C1801024L-70T

Ultra Low Power 128K x 8 CMOS SRAM

Mosel Vitelic Corporation  

V62C1801024L(L)

Timing Waveform of Write Cycle 1 (10,11) (WE Controlled)

Address

tAW

tWC

tWR

WE

tWP

DIN

DOUT

tAS

tDW

tDH

Data Valid

tWZ

tOW

Timing Waveform of Write Cycle 2 (10,11) (CE1 Controlled)

tWC

tAW

tWR

Address

CE1

tAS

tCW

WE

tWP

DIN

tWZ

tDW

tDH

Data Valid

DOUT

Timing Waveform of Write Cycle 3 (10,11) (CE2 Controlled)

tWC

tAW

tWR

Address

tAS

tCW

CE2

tWP

WE

tWZ

tDW

tDH

DIN

Data Valid

DOUT

REV. 1.1 April 2001 V62C1801024L(L)

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