WM8976 データシートの表示（PDF） - Wolfson Microelectronics plc

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WM8976

Stereo CODEC With Speaker Driver

Wolfson Microelectronics plc 

WM8976

Pre-Production

The polarity of the output signal can also be changed under software control using the ADCLPOL

register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit.

With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when

ADCOSR=1 the oversample rate is 128x which gives best performance.

REGISTER

ADDRESS

R14

ADC Control

BIT

LABEL

0

ADCLPOL

3

ADCOSR

Table 12 ADC Control

DEFAULT

DESCRIPTION

0

ADC polarity adjust:

0=normal

1=inverted

0

ADC oversample rate select:

0=64x (lower power)

1=128x (best performance)

SELECTABLE HIGH PASS FILTER

A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two

modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off

frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off

frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown

in Table 14.

REGISTER

ADDRESS

R14

ADC Control

BIT

LABEL

8

HPFEN

7

HPFAPP

6:4

HPFCUT

Table 13 ADC Enable Control

DEFAULT

DESCRIPTION

1

High Pass Filter Enable

0=disabled

1=enabled

0

Select audio mode or application mode

0=Audio mode (1st order, fc = ~3.7Hz)

1=Application mode (2nd order, fc =

HPFCUT)

000

Application mode cut-off frequency

See Table 14 for details.

HPFCUT

[2:0]

SR=101/100

8 11.025 12

SR=011/010

fs (kHz)

16 22.05 24

SR=001/000

32 44.1 48

000

82

113 122 82 113 122 82 113 122

001

102 141 153 102 141 153 102 141 153

010

131 180 156 131 180 156 131 180 156

011

163 225 245 163 225 245 163 225 245

100

204 281 306 204 281 306 204 281 306

101

261 360 392 261 360 392 261 360 392

110

327 450 490 327 450 490 327 450 490

111

408 563 612 408 563 612 408 563 612

Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1). Values in Hz.

Note that the High Pass filter values (when HPFAPP=1) are calculated with the assumption that the

SR register bits are set correctly for the actual sample rate as shown in Table 14.

w

PP Rev 3.0 April 2006

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