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SAF-XC164CS-32F20F データシートの表示(PDF) - Infineon Technologies

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SAF-XC164CS-32F20F
Infineon
Infineon Technologies 
SAF-XC164CS-32F20F Datasheet PDF : 80 Pages
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XC164-32
Derivatives
General Device Information
Table 2
Pin Definitions and Functions
Sym- Pin Input Function
bol
Num. Outp.
RSTIN 1
I
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the XC164.
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Note: The reset duration must be sufficient to let the
hardware configuration signals settle.
External circuitry must guarantee low level at the
RSTIN pin at least until both power supply voltages
have reached the operating range.
P20.12 2
IO
For details, please refer to the description of P20.
NMI 3
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC164 into power down
mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
P0H.0 - 4 … 7 IO
P0H.3
For details, please refer to the description of PORT0.
Data Sheet
9
V1.0, 2005-06

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