MC14013B
20 ns
D
tsu (H)
C
90%
50%
10%
tsu (L)
th
tWH
tPLH
Q
1
fcl
90%
50%
10%
20 ns
90%
50%
10%
tWL
VDD
VSS
20 ns
VDD
VSS
tPHL
VOH
VOL
tTLH
tTHL
Inputs R and S low.
Figure 1. Dynamic Signal Waveforms
(Data, Clock, and Output)
20 ns
SET OR
RESET
90%
tw
CLOCK
tPLH
tPHL
Q OR Q
20 ns
50%
10%
20 ns
90%
trem
50%
tw
50%
VDD
VSS
20 ns VDD
10%
VSS
VOH
VOL
Figure 2. Dynamic Signal Waveforms
(Set, Reset, Clock, and Output)
D
CLOCK
CLOCK
TYPICAL APPLICATIONS
n−STAGE SHIFT REGISTER
1
2
D
Q
D
Q
C
Q
C
Q
nth
D
Q
Q
C
Q
BINARY RIPPLE UP−COUNTER (Divide−by−2n)
1
2
nth
D
Q
D
Q
D
Q
Q
C
Q
C
Q
C
Q
T FLIP-FLOP
CLOCK
MODIFIED RING COUNTER (Divide−by−(n+1))
1
2
nth
D
Q
D
Q
D
Q
Q
C
Q
C
Q
C
Q
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