74HC4024D,653 データシートの表示（PDF） - NXP Semiconductors.
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74HC4024D,653 Datasheet PDF : 19 Pages
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NXP Semiconductors
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7.
Symbol Parameter
Conditions
fmax
maximum frequency CP; see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
12. Waveforms
74HC4024
7-stage binary ripple counter
Min
Typ
Max
Unit
4.0
-
-
MHz
20
-
-
MHz
24
-
-
MHz
MR input
VM
CP input
tPHL
Q0 or Qn
output
tW
1/fmax
trec
VM
10 %
tPLH
90 %
tTLH
tW
90 %
tPHL
VM
10 %
tTHL
001aab910
Fig 6.
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to
clock (CP) recovery time.
VM = 0.5 VI.
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
74HC4024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 23 August 2012
© NXP B.V. 2012. All rights reserved.
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