5962-9685201KYC データシートの表示（PDF） - Avago Technologies

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5962-9685201KYC

Intelligent Power Module and Gate Drive Interface Hermetically Sealed Optocouplers

Avago Technologies 

Switching Specifications (RL= Internal Pull-up)

Over recommended operating conditions: (TA = -55°C to +125°C, VCC = +4.5 V to 30 V, IF(ON) = 10 mA to 20 mA,

VF(OFF) = -5 V to 0.8 V) unless otherwise specified.

Parameter

Group A

Symbol Subgrps.[12] Min. Typ.* Max. Units Test Conditions

Fig. Note

Propagation Delay tPHL

Time to Low

Output Level

Propagation Delay tPLH

Time to High

Output Level

9, 10, 11 20 185 500 ns

9, 10, 11 220 415 750 ns

IF(on) = 10 mA,

VF(off ) = 0.8 V,

VCC = 15.0 V,

CL = 100 pF,

VTHLH = 2.0 V

VTHHL = 1.5 V

5, 8, 3, 4, 5,

6, 7

Pulse Width Distortion PWD

9, 10, 11

150 600 ns

11

Propagation Delay tPLH -tPHL 9, 10, 11

-225 150 650 ns

8

Difference Between

Any Two Parts

Output High Level

Common Mode

Transient Immunity

Output Low Level

Common Mode

Transient Immunity

|CMH|

|CML|

10

kV/s IF = 0 mA, VCC = 15.0 V, 6, 21 9

VO > 3.0 V CL = 100 pF,

VCM = 1000 VP-P

10

kV/s IF = 16 mA TA = 25° C

10

VO < 1.0 V

Power Supply

PSR

Rejection

1.0

VP-P

Square Wave, tRISE, tFALL > 5 ns,

7

no bypass capacitors.

*All typical values at 25° C, VCC = 15 V.

Notes:

1. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO) to the forward LED input current (IF) times 100.

2. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together and Pins 5, 6, 7 and 8 shorted together.

3. Pulse: f = 20 kHz, Duty Cycle = 10%

4. The internal 20 k resistor can be used by shorting pins 6 and 7 together.

5. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved

by using an external 20 k 1% load resistor. For more information on how propagation delay varies with load resistance, see Figure 8.

6. The RL = 20 k, CL = 100 pF represents a typical IPM (Intelligent Power Module) load.

7. Use of a 0.1 F bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise.

8. The difference in tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications

section.)

9. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the

output will remain in a Logic High state (i.e., VO > 3.0 V).

10. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the

output will remain in a Logic Low state (i.e., VO < 1.0 V).

11. Pulse Width Distortion (PWD) is defined as the difference between tPLH and tPHL for any given device.

12. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25° C, +125° C, and -55° C (Subgroups

1 and 9, 2 and 10, 3 and 11 respectively).

13. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified

for all lots not specifically tested.

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