ADUC812(1999) データシートの表示（PDF） - Analog Devices

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ADUC812
(Rev.:1999)

MicroConverter™, Multichannel 12-Bit ADC with Embedded FLASH MCU

Analog Devices 

ADuC812

IE

EA

EADC

ET2

ES

ET1

EX1

ET0

EX0

INTERRUPT ENABLE REGISTER #1

ENABLE INTURRUPTS

(0 = ALL INTERRUPTS DISABLED)

ENABLE ADCI (ADC INTERRUPT)

ENABLE TF2/EXF2

(TIMER2 OVERFLOW INTERRUPT)

ENABLE RI/TI (SERIAL PORT INTERRUPT)

ENABLE TF1 (TIMER1 OVERFLOW INTERRUPT)

ENABLE IE1 (EXTERNAL INTERRUPT 1)

ENABLE TFO (TIMER0 OVERFLOW INTERRUPT)

ENABLE IE0 (EXTERNAL INTERRUPT 0)

IE2

IE2.1

IE2.0

INTERRUPT ENABLE REGISTER #2

ENABLE PSMI

(POWER SUPPLY MONITOR INTERRUPT)

ENABLE ISPI/I2CI

(SERIAL INTERFACE INTERRUPT)

IP

PSI

PADC

PT2

PS

PT1

PX1

PT0

PX0

INTERRUPT PRIORITY REGISTER

PRIORITY OF ISI/ISPI

(SERIAL INTERFACE INTERRUPT)

PRIORITY OF ADCI (ADC INTERRUPT)

PRIORITY OF TF2/EXF2

(TIMER2 OVERFLOW INTERRUPT)

PRIORITY OF RI/TI (SERIAL PORT INTERRUPT)

PRIORITY OF TF1

(TIMER1 OVERFLOW INTERRUPT)

PRIORITY OF IE1 (EXTERNAL INT1)

PRIORITY OF TF0

(TIMER0 OVERFLOW INTERRUPT)

PRIORITY OF IE0 (EXTERNAL INT0)

TMOD TIMER MODE REGISTER

TMOD.3/.7

TMOD.2/.6

TMOD.1/.5

TMOD.0/.4

GATE CONTROL BIT (0 = IGNORE INTx)

COUNTER/TIMER SELECT BIT (0 = TIMER)

TIMER MODE SELECTON BITS

[13 BIT T, 16 BIT T/C, 8 BIT T/C RELOAD,

2 ؋ 8 BIT T]

(UPPER NIBBLE = TIMER1, LOWER NIBBLE = TIMER2)

TCON

TIMER CONTROL REGISTER

TF1 TIMER1 OVERFLOW FLAG

(AUTO CLEARED ON VECTOR TO ISR)

TR1 TIMER1 RUN CONTROL (0 = OFF, 1 = RUN)

TF0 TIMER0 OVERFLOW FLAG

(AUTO CLEARED ON VECTOR TO ISR)

TR0 TIMER0 RUN CONTROL (0 = OFF, 1 = RUN)

IE1

EXTERNAL INT1 FLAG

(AUTO CLEARED ON VECTOR TO ISR)

IT1

IE1 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)

IE0

EXTERNAL INT0 FLAG

(AUTO CLEARED ON VECTOR TO ISR)

IT0

IE0 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)

TH0, TL0 TIMER0 REGISTERS

TH1, TL1 TIMER1 REGISTERS

T2CON TIMER2 CONTROL REGISTER

TF2 OVERFLOW FLAG

EXF2 EXTERNAL FLAG

RCLK RECEIVE CLOCK ENABLE

(0 = TIMER1 USED FOR RxD CLK)

TCLK TRANSMIT CLOCK ENABLE

(0 = TIMER1 USED FOR TxD CLK)

EXEN2 EXTERNAL ENABLE

(0 = IGNORE T2EX, 1 = CAP/RL)

TR2 RUN CONTROL (0 = STOP, 1 = RUN)

CNT2 TIMER/COUNTER SELECT

(0 = TIMER, 1 = COUNTER)

CAP2 CAPTURE/RELOAD SELECT

(0 = RELOAD, 1 = CAPTURE)

TH2, TL2 TIMER2 REGISTER

RCAP2H, RCAP2L TIMER2 CAPTURE/RELOAD

SPICON SPI CONTROL REGISTER

ISPI

WCOL

SPE

SPIM

CPOL

CPHA

SPR1

SPR0

SPI INTERRUPT

(SET AT END OF SPI TRANSFER)

WRITE COLLISION ERROR FLAG

SPI ENABLE

(0 = DISABLE, ALSO ENABLES SPI)

MASTER MODE SELECT (0 = SLAVE)

CLOCK POLARITY SELECT

(0 = SCLK IDLES LOW)

CLOCK PHASE SELECT

(0 = LEADING EDGE LATCH)

SPI BITRATE SELECT BITS

BITRATE = FOSC / [4, 8, 32, 64]

SPIDAT SPI DATA REGISTER

I2CCON I2C CONTROL REGISTER

MDO

MDE

MCO

MDI

I2CM

I2CRS

I2CTX

I2CI

MASTER MODE SDATA OUTPUT BIT

MASTER MODE SDATA OUTPUT

ENABLE

MASTER MODE SCLK BIT

MASTER MODE SDATA INPUT BIT

MASTER MODE SELECT

SERIAL PORT RESET

TRANSMISSION DIRECTION STATUS

SERIAL INTERFACE INTERRUPT

I2CADD I2C ADDRESS REGISTER

I2CDAT I2C DATA REGISTER

Figure 19. Interrupt, Timer, SPI and I2C Control SFRs

–20–

REV. 0

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