HI-8571PDI データシートの表示（PDF） - Holt Integrated Circuits
部品番号
コンポーネント説明
メーカー
HI-8571PDI Datasheet PDF : 9 Pages
| |||
HI-8570, HI-8571
FUNCTIONAL DESCRIPTION
Figure 1 is a block diagram of the line driver. The +5V and
-5V levels are generated from the supply voltages. Cur-
rents for slope control are set by zener voltages across on-
chip resistors.
The TX0IN and TX1IN inputs receive logic signals from a
control transmitter chip such as the HI-6010, HI-3282, HI-
8282A, HI-8584 or HI-8783. TXAOUT and TXBOUT hold
each side of the ARINC bus at Ground until one of the
inputs becomes a One. If for example TX1IN goes high, a
charging path is enabled to 5V on an “A” side internal
capacitor while the “B” side is enabled to -5V. The charg-
ing current is selected by the SLP1.5 pin. If the SLP1.5
pin is high, the capacitor is nominally charged from 10% to
90% in 1.5µs. If SLP1.5 is low, the rise and fall times are
10µs.
A unity gain buffer receives the internally generated slopes
and differentially drives the ARINC line. Current is limited
by the series output resistors at each pin. There are no
fuses at the outputs of the HI-8570 as exists on the HI-
8382.
The HI-8570 has 37.5 ohms in series with each output and
the HI-8571 has 27.5 ohms in series with each output.
The HI-8571 is for applications where external series re-
sistance is required, typically for lightning protection de-
vices.
Both the HI-8570 and HI-8571 are built using high-speed
CMOS technology. Care should be taken to ensure the
V+ and V- supplies are locally decoupled and that the
input waveforms are free from negative voltage spikes
which may upset the chip’s internal slope control circuitry.
TX0IN
TX1IN
ESD
PROTECTION
AND
VOLTAGE
TRANSLATION
ONE
NULL
ZERO
CONTROL
LOGIC
5V
“A” SIDE
CURRENT
CONTROL
-5V
SLP1.5
HI-8570 = 37.5 OHMS
HI-8571 = 27.5 OHMS
TXAOUT
ONE
NULL
ZERO
CONTROL
LOGIC
5V
“B” SIDE
CURRENT
CONTROL
-5V
HI-8570 = 37.5 OHMS
HI-8571 = 27.5 OHMS
FIGURE 1 - LINE DRIVER BLOCK DIAGRAM
TXBOUT
APPLICATION INFORMATION
Figure 2 shows a possible application
of the HI-8570/8571 interfacing an
ARINC transmit channel from the HI-
6010.
HARDWIRED
OR
{
DRIVEN FROM LOGIC
ARINC
Channel
ARINC
Channel
5V
1
2
VCC
TESTA
ROUTA
6
8
TESTB
7
ROUTB
4 HI-8588
RINA
3
RINB
5
5V
1
8
SLP1.5
6 TXAOUT
V+
3
TX1IN
7 HI-8570 2
TXBOUT
TX0IN
GND
V-
45
RXD1
RXD0
HI-6010
8 BIT BUS
TXD1
TXD0
-5V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
Share Link: 