MLD1N06CLT4G(2017) データシートの表示（PDF） - ON Semiconductor
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MLD1N06CLT4G Datasheet PDF : 8 Pages
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MLD1N06CL
PULSE GENERATOR
Rgen
50W
VDD
RL
Vout
Vin
DUT
z = 50 W
50 W
td(on)
ton
tr
90%
td(off)
OUTPUT, Vout
10%
INVERTED
INPUT, Vin
50%
10%
PULSE WIDTH
toff
tf
90%
90%
50%
Figure 10. Switching Test Circuit
Figure 11. Switching Waveforms
ACTIVE CLAMPING
The technology can provide on−chip realization of the
popular gate−to−source and gate−to−drain Zener diode
clamp elements. Until recently, such features have been
implemented only with discrete components which
consume board space and add system cost. The technology
approach economically melds these features and the power
chip with only a slight increase in chip area.
In practice, back−to−back diode elements are formed in a
polysilicon region monolithicly integrated with, but
electrically isolated from, the main device structure. Each
back−to−back diode element provides a temperature
compensated voltage element of about 7.2 V. As the
polysilicon region is formed on top of silicon dioxide, the
diode elements are free from direct interaction with the
conduction regions of the power device, thus eliminating
parasitic electrical effects while maintaining excellent
thermal coupling.
To achieve high gate−to−drain clamp voltages, several
voltage elements are strung together; the MLD1N06CL uses
8 such elements. Customarily, two voltage elements are used
to provide a 14.4 V gate−to−source voltage clamp. For the
MLD1N06CL, the integrated gate−to−source voltage
elements provide greater than 2.0 kV electrostatic voltage
protection.
The avalanche voltage of the gate−to−drain voltage clamp
is set less than that of the power MOSFET device. As soon
as the drain−to−source voltage exceeds this avalanche
voltage, the resulting gate−to−drain Zener current builds a
gate voltage across the gate−to−source impedance, turning
on the power device which then conducts the current. Since
virtually all of the current is carried by the power device, the
gate−to−drain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
drain−to−source sustaining voltage (Figure 7) effectively
removes the possibility of drain−to−source avalanche in the
power device.
The gate−to−drain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gate−to−drain clamped
conduction mode rather than in the more stressful
gate−to−source avalanche mode.
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS
The MLD1N06CL has been designed to allow direct
VBAT
interface to the output of a microcontrol unit to control an
isolated load. No additional series gate resistance is required,
VDD
but a 40 kW gate pulldown resistor is recommended to avoid
a floating gate condition in the event of an MCU failure. The
internal clamps allow the device to be used without any
D
external transistent suppressing components.
MCU
G
MLD1N06CL
S
www.onsemi.com
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