VG3617161DT データシートの表示（PDF） - Vanguard International Semiconductor
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VG3617161DT Datasheet PDF : 70 Pages
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VIS
Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
Capacitance
(Ta=25°C,f=1MHZ)
Parameter
Symbol
Typ
Input capacitance(CLK)
C11
2.5
Input capacitance(all input pins except data
C12
2.5
pins)
Data input/output capacitance
CI/O
4.0
Max
Unit
4
pF
5
pF
6.5
pF
Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, Ta = 0 ~ 70°C)
Description/test condition
-5.5
-6
-7
-8
Unit Note
Symbol Min. Max. Min. Max. Min. Max. Min. Max.
Operating Current
tRC ≥ tRC(min), Outputs Open
Address changed once during tCK(min).
Burst Length = 1 (One Bank Active)
IDD1
190
185
165
145
3,4
Precharge Standby Current in non power-down mode IDD2N
95
85
75
65
3
tCK = tCK(min), CS ≥ VIH(min), CKE ≥ VIH (min)
Input signals are changed once during 30ns.
Precharge Standby Current in non power-down mode IDD2NS
45
40
35
30
tCK = ∞ , CKE ≥ VIH (min), CLK ≤ VIL (max)
mA
Input signals are stable
Precharge Standby Current in power-down mode
IDD2P
4
4
4
4
3
tCK = tCK(min), CKE ≤ VIL (max)
Precharge Standby Current in power-down mode
IDD2PS
3.5
3.5
3.5
3.5
tCK = ∞ , CKE ≤ VIL (max), CLK ≤ VIL (max)
Active Standby Current in non power down mode
IDD3N
85
75
65
55
3
CKE ≥ VIH (min), tCK = tCK(min)(Both Bank Actioe)
Active Standby Current in power-down
IDD3P
6
6
6
6
CKE ≤ VIL (max), tCK = tCK(min), CS ≥ VIH(min)(Both
Bank Active)
Operating Current (Page Burst, and All Bank activated) IDD4
195
185
175
165
4,5
tCCD = tCCD(min), Outputs Open, Multi-bank interleave,
gapless data
Refresh Current
tRC ≥ tRC (min) (tREF = 64ms)
IDD5
185
175
165
155
3
Self Refresh Current
CKE ≤ 0.2V
IDD6
4
4
4
4
Document:1G5-0160
Rev.1
Page 5
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