CXK77B1810AGB データシートの表示（PDF） - Sony Semiconductor
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CXK77B1810AGB Datasheet PDF : 4 Pages
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Pin Configuration (Top View)
1
A VDDQ
B NC
C NC
D DQb
E NC
F VDDQ
G NC
H DQb
J VDDQ
K NC
L DQb
M VDDQ
N DQb
P NC
R NC
T NC
U VDDQ
2
A
NC
A
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQb
A
A
TMS
3
A
NC
A
VSS
VSS
VSS
BWb
VSS
VREF
VSS
VSS
VSS
VSS
VSS
M1
A
TDI
4
NC
NC
VDD
ZQ
S
G
C
C
VDD
K
K
W
A
A
VDD
NC
TCK
5
A
NC
A
VSS
VSS
VSS
VSS
VSS
VREF
VSS
BWa
VSS
VSS
VSS
M2
A
TDO
6
A
NC
A
DQa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
CXK77B1810AGB
Pin Description
Symbol
Description
A
Address Input
DQx
K
K
Data I/O in byte
(a to b)
Positive Clock
Negative Clock
Symbol
Description
BWX
Byte Write Enable
(a to b)
S
Chip Select
G
Asyn Output Enable
ZZ
Sleep Mode Select
C
Output Positive Clock(∗) TCK
JTAG Clock
Output Negative
C
Clock(∗)
TMS JTAG Mode Select
VREF Input Reference
TDI
JTAG Data In
W
Write Enable
TDO JTAG Data Out
(∗) These pins should be tied to VDD or VSS except D-C mode.
Symbol
Description
VDD
+3.3V power supply
VDDQ Output power supply
VSS
Ground
M1, M2 Mode Select
ZQ
Output Impedance
Control
NC
No Connect
–3–
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