DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

AD1895YRS データシートの表示(PDF) - Analog Devices

部品番号
コンポーネント説明
メーカー
AD1895YRS Datasheet PDF : 24 Pages
First Prev 21 22 23 24
AD1895
TDM MODE APPLICATION
In TDM mode, several AD1895s can be daisy-chained together
and connected to the serial input port of a SHARC® DSP. The
AD1895 contains a 64-bit parallel load shift register. When the
LRCLK_O pulse arrives, each AD1895 parallel loads its left and
right data into the 64-bit shift register. The input to the shift
register is connected to TDM_IN while the output is connected
to SDATA_O. By connecting the SDATA_O to the TDM_IN
of the next AD1895, a large shift register is created which is
clocked by SCLK_O.
The number of AD1895s that can be daisy-chained together is
limited by the maximum frequency of SCLK_O, which is about
25 MHz. For example, if the output sample rate, fS, is 48 kHz,
up to eight AD1895s could be connected since 512 × fS is less
than 25 MHz. In Master/TDM Mode, the number of AD1895s
that can be daisy-chained is fixed to four.
LRCLK
SCLK
AD1895
TDM_IN
SDATA_O
LRCLK_O
SCLK_O
AD1895
TDM_IN
SDATA_O
LRCLK_O
SCLK_O
AD1895
TDM_IN
SDATA_O
LRCLK_O
SCLK_O
SHARC
DSP
DR0
RFS0
RCLK0
SLAVE-1
M2 M1 M0
SLAVE-2
M2 M1 M0
SLAVE-n
M2 M1 M0
0
0
0
0
0
0
0
0
0
STANDARD MODE
Figure 11. Daisy-Chain Configuration for TDM Mode (All AD1895s Being Clock-Slaves)
AD1895
TDM_IN
SDATA_O
LRCLK_O
SCLK_O
AD1895
TDM_IN
SDATA_O
LRCLK_O
SCLK_O
AD1895
TDM_IN
SDATA_O
LRCLK_O
SCLK_O
SHARC
DSP
DR0
RFS0
RCLK0
CLOCK-MASTER
M2 M1 M0
SLAVE-1
M2 M1 M0
SLAVE-n
M2 M1 M0
0
1
1
0
0
0
0
0
0
STANDARD MODE
Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1895 Being Clock-Master)
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
–21–

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]