MK10DX2M0AVFM12 データシートの表示（PDF） - Freescale Semiconductor

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MK10DX2M0AVFM12

K10 Sub-Family

Freescale Semiconductor 

Peripheral operating requirements and behaviors

SDHC_CLK

SD3

SD2

SD1

SD6

Output SDHC_CMD

Output SDHC_DAT[3:0]

Input SDHC_CMD

SD7

SD8

Input SDHC_DAT[3:0]

Figure 25. SDHC timing

6.8.7 I2S/SAI switching specifications

This section provides the AC timing for the I2S/SAI module in master mode (clocks are

driven) and slave mode (clocks are input). All timing is given for noninverted serial clock

polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]

is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been

inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the

frame sync (FS) signal shown in the following figures.

6.8.7.1 Normal Run, Wait and Stop mode performance over a limited

operating voltage range

This section provides the operating performance over a limited operating voltage for the

device in Normal Run, Wait and Stop modes.

Table 44. I2S/SAI master mode timing in Normal Run, Wait and Stop modes

(limited voltage range)

Num.

S1

S2

S3

S4

S5

Characteristic

Operating voltage

I2S_MCLK cycle time

I2S_MCLK pulse width high/low

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

Min.

2.7

40

45%

80

45%

—

Table continues on the next page...

Max.

3.6

—

55%

—

55%

15

Unit

V

ns

MCLK period

ns

BCLK period

ns

K10 Sub-Family Data Sheet, Rev. 3, 6/2013.

62

Freescale Semiconductor, Inc.

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