MACH111SP-18YI/1 データシートの表示（PDF） - Lattice Semiconductor
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MACH111SP-18YI/1 Datasheet PDF : 48 Pages
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MACH221 and MACH221SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1
Parameter
Symbol
Parameter Description
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
7.5
10
12
14
15
18 ns
ts
Setup Time from Input, I/O, or Feedback to D-type 5.5
6.5
Clock
T-type 6.5
7.5
7
8
8.5
10
12
10
11
13.5
ns
ns
tH
Register Data Hold Time
0
0
0
0
0
0
ns
tCO
Clock to Output
5
6
8
10
10
12 ns
tWL
Clock Width
tWH
LOW
3
5
6
6
6
7.5
ns
HIGH
3
5
6
6
6
7.5
ns
External
D-type 95
80
66.7
54
50
42
MHz
Feedback
1/(tS + tCO)
T-type
87
74
62.5
50
47.6
39
MHz
fMAX
Maximum
Frequency
D-type 133
Internal Feedback (fCNT) T-type
125
100
91
83.3
69
66.6
55.6
76.9
62.5
62.5
51.3
MHz
MHz
No Feedback 1/(tWL + tWH)
167
100
83.3
83.3
83.3
66.7
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
5.5
6.5
7
8.5
10
12
ns
tHL
Latch Data Hold Time
0
0
0
0
0
0
ns
tGO
Gate to Output
7
7
10
11
11
13.5 ns
(note 2)
tGWL
Gate Width LOW
3
5
6
6
6
7.5
ns
tPDL
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
9.5
12
14
17
17
20.5 ns
tSIR
Input Register Setup Time
2
2
2
2
2
2.5
ns
tHIR
Input Register Hold Time
2
2
2
2.5
2.5
3.5
ns
tICO
Input Register Clock to Combinatorial Output
11
13
15
18
18
22 ns
D-type 9
10
12
14.5
15
18
ns
tICS
Input Register Clock to Output Register Setup
T-type 10
11
13
16
16
19.5
ns
tWICL
Input Register
LOW
3
5
6
6
6
7.5
ns
tWICH
Clock Width
HIGH
3
5
6
6
6
7.5
ns
fMAXIR
Maximum Input Register
Frequency
1/(tWICL + tWICH)
167
100
83.3
83.3
83.3
66.7
MHz
tSIL
Input Latch Setup Time
2
2
2
2
2
2.5
ns
tHIL
Input Latch Hold Time
2
2
2
2.5
2.5
3.5
ns
tIGO
Input Latch Gate to Combinatorial Output
12
14
17
20
20
24 ns
tIGOL
Input Latch Gate to Output Through Transparent Output
Latch
14
16
19
22
22
26.5 ns
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7.5
8.5
9
11
12
14.5
ns
tIGS
Input Latch Gate to Output Latch Setup
10
11
13
16
16
19.5
ns
tWIGL
Input Latch Gate Width LOW
3
5
6
6
6
7.5
ns
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
11.5
14
16
19
19
23 ns
tAR
Asynchronous Reset to Registered or Latched Output
9.5
15
16
19.5
20
24 ns
tARW
Asynchronous Reset Width (Note 3)
5
10
12
14.5
15
18
ns
tARR
Asynchronous Reset Recovery Time (Note 3)
5
8
10
10
10
12
ns
tAP
Asynchronous Preset to Registered or Latched Output
9.5
15
16
19.5
20
24 ns
MACH 1 & 2 Families
29
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