IDT70261L(2000) データシートの表示（PDF） - Integrated Device Technology

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IDT70261L
(Rev.:2000)

HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT

Integrated Device Technology 

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)

tWC

ADDR"A"

MATCH

tWP

R/W"A"

tDW

tDH

DATAIN "A"

tAPS (1)

VALID

ADDR"B"

BUSY"B"

tBAA

MATCH

tBDA

tBDD

tWDD

DATAOUT "B"

tDDD (3)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

VALID

3039 drw 11

Timing Waveform of Write with BUSY (M/S = VIL)

tWP

R/W"A"

BUSY"B"

tWB(3)

tWH (1)

R/W"B"

(2)

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the “SLAVE” version.

,

3039 drw 12

61.422

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