IDT70261L(2000) データシートの表示（PDF） - Integrated Device Technology

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IDT70261L
(Rev.:2000)

HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT

Integrated Device Technology 

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Waveform of Read Cycles(5)

tRC

ADDR

tAA (4)

CE

tACE (4)

tAOE (4)

OE

UB, LB

tABE (4)

Industrial and Commercial Temperature Ranges

R/W

DATAOUT

BUSYOUT

tLZ (1)

VALID DATA(4)

tBDD (3, 4)

tOH

tHZ (2)

3039 drw 05

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

ICC

50%

ISB

tPD

50%

,

3039 drw 06

6.742

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