M62333P(2007) データシートの表示（PDF） - Renesas Electronics

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M62333P
(Rev.:2007)

8-bit 3ch I2C BUS D/A Converter with Buffer Amplifiers

Renesas Electronics 

M62333P/FP, M62338P/FP

Timing Chart (Model)

<Start condition to slave address bit>

SDA

1

2

3

4

5

6

7

W

A

SCL

D/A

output

Start condition

<Sub address bit>

SDA

1

2

3

4

5

6

7

8

A

SCL

D/A

output

<DAC data bit to stop condition>

SDA

1

2

3

4

5

6

7

8

A

SCL

D/A

output

Stop

condition

• Start condition

With SCL at High, SDA line goes from High to Low

• Stop condition

With SCL at High, SDA line goes from Low to High

(Under normal circumstances, SDA is changed when SCL is Low)

• Acknowledge bit The receiving IC has to pull down SDA line whenever receive slave data.

(The transmitting IC releases the SDA line just then transmit 8-bit data.)

Digital Data Formats

STA

Slave address

WA

Sub address 1

A

DAC data 1

A …………

Sub address 2

A

DAC data 2

A

Sub address n

A

DAC data n

A STP

REJ03D0865-0300 Rev.3.00 Jun 15, 2007

Page 6 of 9

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