FX641P4 データシートの表示（PDF） - CML Microsystems Plc

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FX641P4

Dual Subscriber Private Metering (SPM) Detector

CML Microsystems Plc 

Pin Number

FX641

D2/P4

13 No internal connection; leave open circuit.

Function

14

Ch 2 Amp In (+): The positive input to the Channel 2 Input Amplifier. See Figures 2 and 3.

15 Ch 2 Amp In (-): The negative input to the Channel 2 Input Amplifier. See Figures 2 and 3.

16

Ch 2 Amp Out: The output of the Channel 2 Input Amplier. See Figures 2 and 3.

17 Output Select: A logic input to set the Channel 1 and Channel 2 output modes.

When high (logic '1'), the outputs are in the Tone Follower mode; when low (logic '0'), the outputs are

in the Packet mode.

18 Preset Level: A logic input to set the sensitivity mode of the FX641.

When high (logic '1'), both channels are in the Fixed Sensitivity mode. The external components

govern the input sensitivity; the System Select input selects 12kHz or 16kHz operation. When low

(logic '0'), both channels are in the Controlled Sensitivity mode. Device sensitivities and system

selection are via the Chip Select/Serial Data/Serial Clock inputs. This input has an internal pullup

resistor on chip (Fixed Sensitivity Mode).

19 Chip Select: The Chip Select input for use in data loading when using the FX641 in the Controlled

Sensitivity mode (see Figure 9).

The device is selected when this input is set low (logic '0').

When the device is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD.

20 Serial Clock: The Serial Clock input for use in data loading when using the FX641 in the Controlled

Sensitivity mode (see Figure 9). Data is loaded to the FX641 on this clock's rising edge.

When the device is in the Fixed Sensitivity mode this input should be connected to either V or V .

SS

DD

21 Serial Data: The Serial Data input for use in data loading when using the FX641 in the Controlled

Sensitivity mode (see Figure 9 and Table 2).

When the device is in the Fixed Sensitivity mode this input should be connected to either VSS or VDD.

22 System Select: In the Fixed Sensitivity mode this pin selects the system frequency.

High (logic ‘1’) = 12kHz; Low (logic ‘0’) = 16kHz.

In the Controlled Sensitivity mode this pin should be tied to Vdd or left unconnected.

This pin has an internal pullup resistor on chip.

23 No internal connection; leave open circuit.

24

VDD: Positive supply rail; a single, stable power supply is required. Critical levels and voltages within

the FX641 are dependant upon this supply. This pin should be decoupled to VSS by a capacitor

mounted close to the pin.

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