SAA7103E/V4,557 データシートの表示（PDF） - NXP Semiconductors.
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SAA7103E/V4,557 Datasheet PDF : 84 Pages
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 44: Copy generation 0, 1, 2 and CG enable registers, subaddresses 2Ah to 2Ch, bit
description
Legend: * = default value after reset.
Subaddress Bit Symbol Access Value Description
2Ch
7
CGEN R/W
copy generation data output
0* disabled
1
enabled
6 to 4 -
R/W 0
must be programmed with logic 0 to ensure
compatibility to future enhancements
3 to 0 CG[19:16] R/W -
LSBs of the respective bytes are encoded
2Bh
7 to 0 CG[15:8]
2Ah
7 to 0 CG[7:0]
immediately after run-in, the MSBs of the
respective bytes have to carry the CRCC bits,
in accordance with the definition of copy
generation management system encoding
format.
Table 45: Output port control register, subaddress 2Dh, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7
VBSEN R/W
pin GREEN_VBS_CVBS provides a
0
component GREEN signal (CVBSEN1 = 0) or CVBS signal
(CVBSEN1 = 1)
1* luminance (VBS) signal
6
CVBSEN1 R/W
pin GREEN_VBS_CVBS provides a
0* component GREEN (G) or luminance (VBS) signal
1
CVBS signal
5
CVBSEN0 R/W
pin BLUE_CB_CVBS provides a
0
component BLUE (B) or color difference BLUE (CB) signal
1* CVBS signal
4
CEN
R/W
pin RED_CR_C provides a
0
component RED (R) or color difference RED (CR) signal
1* chrominance signal (C) as modulated subcarrier for
S-video
3
ENCOFF R/W
encoder
0* active
1
bypass, DACs are provided with RGB signal after cursor
insertion block
2
CLK2EN R/W
pin TTXRQ_XCLKO2 provides
0
teletext request signal (TTXRQ)
1* buffered crystal clock divided by two (13.5 MHz)
1 and 0 -
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
SAA7102_SAA7103_4
Product data sheet
Rev. 04 — 18 January 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
48 of 84
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