SAA7103E/V4,557 データシートの表示（PDF） - NXP Semiconductors.
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SAA7103E/V4,557 Datasheet PDF : 84 Pages
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Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 49: VPS enable, input control 2, subaddress 54h, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7
VPSEN R/W
video programming system data insertion
0* is disabled
1
in line 16 is enabled
6 to 2 -
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
1
EDGE2 R/W
internal PPD2 data is sampled with
0
rising clock edges
1* falling clock edges; see Table 28 to Table 34
0
EDGE1 R/W
internal PPD1 data is sampled with
0* rising clock edges
1
falling clock edges; see Table 28 to Table 34
Table 50: VPS byte 5, 11, 12, 13 and 14 registers, subaddresses 55h to 59h, bit
description [1]
Subaddress Bit Symbol Access Value Description
55h
7 to 0 VPS5[7:0] R/W -
fifth byte of video programming system data
56h
7 to 0 VPS11[7:0] R/W -
eleventh byte of video programming system
data
57h
7 to 0 VPS12[7:0] R/W -
twelfth byte of video programming system
data
58h
7 to 0 VPS13[7:0] R/W -
thirteenth byte of video programming system
data
59h
7 to 0 VPS14[7:0] R/W -
fourteenth byte of video programming system
data
[1] In line 16; LSB first; all other bytes are not relevant for VPS.
Table 51: Chrominance phase register, subaddress 5Ah, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7 to 0 CHPS[7:0] R/W
00h* phase of encoded color subcarrier (including burst) relative
to horizontal sync; can be adjusted in steps of
360/256 degrees
6Bh PAL B/G and data from input ports in Master mode
16h PAL B/G and data from look-up table
25h NTSC M and data from input ports in Master mode
46h NTSC M and data from look-up table
SAA7102_SAA7103_4
Product data sheet
Rev. 04 — 18 January 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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