MAX8655ETN データシートの表示（PDF） - Maxim Integrated
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MAX8655ETN Datasheet PDF : 23 Pages
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Highly Integrated, 25A, Wide-Input,
Internal MOSFET, Step-Down Regulator
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low losses and
clean, stable operation. Refer to the MAX8655
Evaluation Kit for an example layout. If it is necessary to
deviate from this layout, follow the procedure below.
Follow these guidelines for good PCB layout:
1) Place IC decoupling capacitors as close as possi-
ble to the IC pins. Separate the power and analog
ground planes. Place the input ceramic decoupling
capacitor directly across and as close as possible
to PVIN and PGND. This is to help contain the high
switching current within this small loop.
2) For output current greater than 10A, a four-layer
PCB is recommended. Pour an analog ground
plane in the second layer underneath the IC to mini-
mize noise coupling.
3) Connect input, output, and VL capacitors to the
power ground plane; connect all other capacitors to
the signal ground plane. Connect analog and
power ground planes at the output capacitor.
4) Place the inductor current-sense resistor and
capacitor as close as possible to the inductor.
Make a Kelvin connection to minimize the effect of
PCB trace resistance. Place the input bias balance
resistor (R2 in Figure 8) near CS-. Run two closely
parallel traces from across capacitor C9 to CS+
and the input bias balance resistor R2.
5) Connect the exposed pad sections to the corre-
sponding IC pins and allow sufficient copper area
to help cooling the device.
6) Place the feedback and compensation components
as close as possible to the IC pins. Connect the
feedback resistor-divider from FB to VOUT as close
as possible to the farthest output capacitor.
PROCESS: BiCMOS
Chip Information
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