ISL54405
Test Circuits and Waveforms (Continued)
FIGURE 1. SWITCHING TIMES
LOGIC
INPUT
VDD
0V
SWITCH
OUTPUT
VOUT 0V
90%
VNX
tD
LOGIC
INPUT
VDD C
Lx
R OR L
Rx
SEL
GND MUTE
VOUT
RL
CL
FIGURE 2A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
SIGNAL
GENERATOR
VDD
C
MUTE
Lx or Rx
rON = V1/80mA
VDD
C
Lx or Rx
ANALYZER
RL
SEL 0V OR VDD
L, R
GND
VNX
80mA
V1
SEL 0V OR VDD
L, R
GND MUTE
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 3. OFF-ISOLATION TEST CIRCUIT
Repeat test for all switches.
FIGURE 4. rON TEST CIRCUIT
SIGNAL
GENERATOR
VDD
C
Lx OR Rx
L, R
SEL
0V OR VDD
L, R
Lx or Rx
ANALYZER
NC
GND MUTE
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CROSSTALK TEST CIRCUIT
IMPEDANCE
ANALYZER
VDD
C
Lx or Rx
SEL 0V OR VDD
L, R
GND MUTE
Repeat test for all switches.
FIGURE 6. CAPACITANCE TEST CIRCUIT
7
FN6699.1
June 5, 2008