AD5251(Rev0) データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
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AD5251
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5251 Datasheet PDF : 28 Pages
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PIN CONFIGURATION AND FUNCTION DESCRIPTION
VDD 1
AD0 2
WP 3
W1 4
B1 5
A1 6
SDA 7
14 W3
AD5251/
AD5252
TOP VIEW
(Not to Scale)
13 B3
12 A3
11 AD1
10 DGND
9 SCL
8 VSS
Figure 2. AD5251/AD5252 in TSSOP-14
AD5251/AD5252
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
VDD
Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply,
where VDD – VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to
EEMEM.
2
AD0
I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252s to be addressed.
3
WP
Write Protect, Active Low. VWP ≤ VDD + 0.3 V.
4
W1
Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.1
5
B1
B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.1
6
A1
A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.1
7
SDA
Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock edges. MSB loaded
first. Open-drain MOSFET requires pull-up resistor.
8
VSS
Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where VDD – VSS ≤
+5.5 V. If VSS is used, other than grounded, in dual supply, VSS must be able to sink 35 mA for
26 ms when storing data to EEMEM.
9
SCL
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. VSCL ≤
(VDD + 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power.
10
DGND
Digital Ground. Connect to system analog ground at a single point.
11
AD1
I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252s to be addressed.
12
A3
A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.1
13
B3
B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.1
14
W3
W Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.1
1 For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.
I2C INTERFACE TIMING DIAGRAM
SCL
t8
t9
t6
t2
t3
t4
t5
t7
t8 t9
SDA
t1
P
S
Figure 3. I2C Timing Diagram
Rev. 0 | Page 9 of 28
t10
P
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