AD9661A
Pin
OUTPUT
POWER LEVEL
CAL
HOLD
PULSE
PULSE 2
SENSE IN
GAIN
POWER MONITOR
DISABLE
VREF
+VS
GROUND
LEVEL SHIFT IN
LEVEL SHIFT OUT
Function
PIN DESCRIPTIONS
Analog laser diode current output. Connect to cathode of laser diode, anode connected to +VS externally.
Analog voltage input, VREF to VREF + 1.6 V. Output current is set proportional to the POWER LEVEL
during
calibration
as follows: IMONITOR
= VPOWER LEVEL – VREF
RGAIN + 50 Ω
TTL/CMOS compatible, feedback loop T/H control signal. Logic LOW enables calibration mode, and
the feedback loop T/H goes into track mode 13 ns after (the aperture delay) PULSE goes logic HIGH
(there is no aperture delay if PULSE goes high before CAL transitions to a LOW level). Logic HIGH dis-
ables the T/H and immediately places it in hold mode. PULSE should be held HIGH while calibrating.
Floats logic HIGH.
External hold capacitor for the bias loop T/H. Approximate droop in the output current while CAL is
logic HIGH is:
± ∆IOUT
= 18 × 10–9 tHOLD
CHOLD
E Bandwidth of the loop is:
BW
≈
2
π
(550
1
Ω)
CHOLD
TTL/CMOS compatible, current control signal. Logic HIGH supplies IOUT to the laser diode. Logic
T LOW turns IOUT off. Floats logic HIGH.
TTL/CMOS compatible, current control signal. Logic LOW supplies IOUT to the laser diode. Logic
HIGH turns IOUT off. Floats logic HIGH.
E Analog current input, IMONITOR, from PIN photo detector diode. SENSE IN should be connected to the
anode of the PIN diode, with the PIN cathode connected to +VS or another positive voltage. Voltage at
SENSE IN varies slightly with temperature and current, but is typically 1.0 V.
L External connection for the feedback network of the transimpedance amplifier. External feedback network,
RGAIN and CGAIN, should be connected between GAIN and POWER MONITOR. See text for choosing
values.
Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from
photo diode, IMONITOR.
O TTL/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH
disables the current outputs to the laser diode, and drives the voltage on the hold capacitors close to VREF
(minimizes the output current when the device is re-enabled). DISABLE floats logic HIGH.
S Analog Voltage output, internal bandgap voltage reference, ~1.8 V, provided to user for power level offset.
Power Supply, nominally +5 V. All +VS connections should be tied together externally.
Ground reference. All GROUND connections should be tied together externally.
B Analog input to the on board level shift circuit. Input Range 0.1 V – 1.6 V.
Voltage output from on board level shift circuit. Connect to POWER LEVEL externally to use the on
board level shift circuit. Output voltage is VLEVEL SHIFT OUT = VLEVEL SHIFT IN +VREF.
O PIN ASSIGNMENTS
PULSE2 1
DNC 2
VREF 3
LEVEL SHIFT IN 4
GAIN 5
POWER MONITOR 6
SENSE INPUT 7
GROUND 8
+VS 9
GROUND 10
HOLD 11
POWER LEVEL 12
LEVEL SHIFT OUT 13
DISABLE 14
AD9661AKR
(Not to Scale)
–4–
28 +VS
27 GROUND
26 OUTPUT
25 GROUND
24 OUTPUT
23 GROUND
22 OUTPUT
21 GROUND
20 OUTPUT
19 GROUND
18 +VS
17 GROUND
16 CAL
15 PULSE1
REV. 0