ADIS16362BMLZ(Rev0) データシートの表示（PDF） - Analog Devices
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ADIS16362BMLZ Datasheet PDF : 20 Pages
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ADIS16362
TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tSTALL
tREADRATE
tCS
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
tSFS
t1
tx
t2
t3
Description
Serial clock
Stall period between data
Read rate
Chip select to clock edge
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise/fall times
DOUT rise/fall times
CS high after SCLK edge
Input sync positive pulse width
Input sync low time
Input sync to data ready output
Input sync period
Normal Mode
Low Power Mode
(SMPL_PRD ≤ 0x09) (SMPL_PRD ≥ 0x0A)
Burst Read
Min1 Typ Max Min1 Typ Max Min1 Typ Max Unit
0.01
2.0 0.01
0.3 0.01
1.0 MHz
9
75
1/fSCLK
μs
40
100
μs
48.8
48.8
48.8
ns
100
100
100 ns
24.4
24.4
24.4
ns
48.8
48.8
48.8
ns
5
12.5
5 12.5
5 12.5 ns
5
12.5
5 12.5
5 12.5 ns
5
5
5
ns
5
5
μs
100
100
μs
600
600
μs
833
833
μs
1 Guaranteed by design and characterization, but not tested in production.
TIMING DIAGRAMS
CS
SCLK
tCS
1
DOUT
MSB
DIN
R/W
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A6
A5
A4
A3
A2
Figure 2. SPI Timing and Sequence
tREADRATE
tSTALL
CS
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
SCLK
Figure 3. Stall Time and Data Rate
SYNC
CLOCK (DIO4)
DATA
READY
t3
t2
t1
tX
Figure 4. Input Clock Timing Diagram
Rev. 0 | Page 5 of 20
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