HEF4017BP データシートの表示（PDF） - NXP Semiconductors.
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HEF4017BP Datasheet PDF : 16 Pages
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NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
VI
CP0 input
VSS
VI
CP1 input
VSS
VI
MR input
VSS
VOH
Q1 - Q9
output
VOL
VOH
Q0, Q5 - Q9
output
VOL
1/f max
tW
VM
1/f max
VM
VM
tW
trec
tW
VM
tPHL
VM
tPLH
001aaj306
Fig 8.
Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition. tW and trec are measured when CP0 = HIGH and
CP1 triggers on a HIGH-to-LOW transition;
The shaded areas indicate where the output state is set by the input count.
Measurement points given in Table 9.
Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for
CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays
VI
CP0 input
VSS
VI
CP1 input
VSS
VM
th
VM
VM
th
VM
001aae578
Fig 9.
Hold times are shown as positive values, but may be specified as negative values;
Measurement points given in Table 9.
Waveforms showing hold times for CP0 to CP1 and CP1 to CP0
Table 9. Measurement points
Supply voltage
VDD
5 V to 15 V
Input
VM
0.5VDD
Output
VM
0.5VDD
HEF4017B_4
Product data sheet
Rev. 04 — 9 December 2008
© NXP B.V. 2008. All rights reserved.
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