PTN3392BS データシートの表示（PDF） - NXP Semiconductors.

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PTN3392BS

2-lane DisplayPort to VGA adapter IC

NXP Semiconductors. 

NXP Semiconductors

PTN3392

2-lane DisplayPort to VGA adapter IC

7.4.1 S0 = logic 0

If S0 is left open-circuit (internal pull-down) (DisplayPort v1.1a compliant behavior),

PTN3392 behaves as stated in VESA DisplayPort v1.1a, sections 7 and 8. PTN3392 will

keep HPD LOW during its internal initialization sequence after power-up. It will then

update DPCD register SINK_COUNT to the expected value, depending if a VGA monitor

is detected or not, and will then assert HPD HIGH whatever is the value of SINK_COUNT

register. Each time PTN3392 detects a change in the VGA monitor connection status, it

updates the SINK_COUNT register accordingly, set

DOWNSTREAM_PORT_STATUS_CHANGED register bit to 1 and generate IRQ_HPD

pulse to signal the source about the status change. Refer to Figure 3, S0 = LOW

flowchart.

7.4.2 S0 = logic 1

If S1 is tied to HIGH with external pull-up (best interoperability behavior), the PTN3392 will

keep HPD LOW during its internal initialization sequence after power-up. It then waits for

a VGA monitor to be connected downstream before asserting HPD HIGH to force source

waiting for a VGA monitor before starting protocol negotiations. If a VGA monitor is

disconnected during normal operations, PTN3392 asserts HPD LOW so that the source

considers that no sink device is connected anymore. Refer to Figure 3, S0 = HIGH

flowchart.

7.5 EDID handling

Figure 4 shows a DisplayPort-to-analog video converter (or dongle) situated between the

DisplayPort source and a VGA monitor. The PTN3392 converts a DP I2C Over AUX

request to I2C on the monitor's DDC bus. The monitor's EDID read data is then returned to

the DP source via an I2C Over AUX response issued by the PTN3392.

It is the responsibility of the source to choose only video modes which are declared in the

EDID and to adjust the DisplayPort link capabilities (link rate and lane count) to provide

the necessary video bandwidth. The PTN3392 does not cache or modify the EDID to

match the capabilities of the DisplayPort link data.

If the DisplayPort source drives display modes that are not specified in the EDID mode

list, the PTN3392 does not detect such conditions, and displays at its output what it is

presented by the DisplayPort source.

source device

DP Tx

box-to-box

DisplayPort

DisplayPort to VGA adapter IC

DP Rx

with DPCD

VIDEO DAC

box-to-box

legacy

sink device

VGA DISPLAY

WITH EDID

002aae039

Fig 4. DisplayPort to VGA adapter IC (dongle) sits between the DisplayPort source and a

VGA monitor with EDID

PTN3392

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 5 June 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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