WM8960CGEFL/2RV データシートの表示（PDF） - Wolfson Microelectronics plc
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WM8960CGEFL/2RV
Wolfson Microelectronics plc
WM8960CGEFL/2RV Datasheet PDF : 91 Pages
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Production Data
REGISTER BIT
ADDRESS
LABEL
R32 (20h) 3
LMIC2B
ADCL Input
Signal Path
6
LMP2
7
LMP3
8
LMN1
R33 (21h) 3
ADCR Input
Signal Path
6
RMIC2B
RMP2
7
RMP3
8
RMN1
Table 3 Input PGA Control
DEFAULT
WM8960
DESCRIPTION
0
Connect Left Input PGA to Left Input Boost
mixer
0 = Not connected
1 = Connected
0
Connect LINPUT2 to non-inverting input of
Left Input PGA
0 = LINPUT2 not connected to PGA
1 = LINPUT2 connected to PGA (Constant
input impedance)
0
Connect LINPUT3 to non-inverting input of
Left Input PGA
0 = LINPUT3 not connected to PGA
1 = LINPUT3 connected to PGA (Constant
input impedance)
1
Connect LINPUT1 to inverting input of Left
Input PGA
0 = LINPUT1 not connected to PGA
1 = LINPUT1 connected to PGA
0
Connect Right Input PGA to Right Input
Boost mixer
0 = Not connected
1 = Connected
0
Connect RINPUT2 to non-inverting input of
Right Input PGA
0 = RINPUT2 not connected to PGA
1 = RINPUT2 connected to PGA (Constant
input impedance)
0
Connect RINPUT3 to non-inverting input of
Right Input PGA
0 = RINPUT3 not connected to PGA
1 = RINPUT3 connected to PGA
(Constant input impedance)
1
Connect RINPUT1 to inverting input of
Right Input PGA
0 = RINPUT1 not connected to PGA
1 = RINPUT1 connected to PGA
INPUT PGA VOLUME CONTROLS
The input PGAs have a gain range from -17.25dB to +30dB in 0.75dB steps. The gains from the
inverting inputs (LINPUT1 and RINPUT1) to the PGA outputs and from the non-inverting inputs
(LINPUT2/RINPUT2 and LINPUT3/RINPUT3) to the PGA output are always common in differential
configuration and controlled by the register bits LINVOL[5:0] and RINVOL[5:0].
When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled automatically
and the LINVOL and RINVOL bits should not be used.
The left and right input PGAs can be independently muted using the LINMUTE and RINMUTE register
bits.
To allow simultaneous volume updates of left and right channels, PGA gains are not altered until a 1
is written to the IPVU bit.
To prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates
will not take place until a zero-crossing is detected. In the event of a long period without zero-
crossings, a timeout function is available. When this function is enabled (using the TOEN register bit),
the volume will update automatically after a timeout. The timeout period is set by TOCLKSEL. Note
that SYSCLK must be running to use this function.
w
PD, August 2013, Rev 4.2
21
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