MC146818AS データシートの表示（PDF） - Motorola => Freescale

部品番号

コンポーネント説明

メーカー

MC146818AS

REAL-TIME CLOCK PLUS RAM

Motorola => Freescale 

~Q– INTERRUPT REQUEST, OUTPUT

The IRQ pin is an active low output of the MC14W18A that

may be used as an interrupt input to a processor, The ~Q

output remains low as long as the status bit causing the in-

terrupt is present and the corresponding interrupt-enable bit

is set. To clear the 1~ pin, the processor program normally

reads Register C. The RESET pin also clears pending inter-

rupts.

When no interrupt conditions are present, the ~Q level is

in the high-impedance state. Multiple interrupting devices

may thus be connected to an ~Q bus with one pullup at the

processor.

FIGURE 12–TYPICAL POWERUP DELAY

CIRCUIT FOR RESET

DI

D2

RESET – RESET, INPUT

The RESET pin does not affect the clock, calendar, or

RAM functions. On powerup, the RESET pin must be held

low for the specified time, tRLH, in order to allow the power

supply to stabilize. Figure 12 shows a typical representation

of the RESET pin circuit.

When RESET is low the following occurs:

a) Periodic Interrupt Enable (PIE) bit is cleared to

zero,

b) Alarm Interrupt Enable (AIE) bit is cleared to zero,

c) Alarm Interrupt Enable (AIE) bit is cleared to zero,

d) Update ended Interrupt Flag (UF) bit is cleared to zero,

e) Interrupt Request status Flag (IRQF) bit is cleared to

zero,

f) Periodic Interrupt Flag ( PF) bit is cleared to zero,

..

.,~!,:~,,+

Not~~${,the RTC is isolated from the MPU or M CU power by a

,~J,,,t dwe drop, care must be taken to meet Vin requirements.

~y 1~~

g) The part is not accessible.

h) Alarm Interrupt Flag (AF) bit is cleared to zero,

i) IRQ pin is in high-impedance

j) Square Wave output Enable

zero,

STBY – STAND– BY

state, and

,,f:~

(SQWE) bit is cleared JQ

,,,.:,*..,Lt.,F..‘F~i.,’,’>,‘+,~\.!lt$~:\;*g*\\$

FIGURE 13 – TYPICAL POWERUP DELAY CIRCUIT

FOR POWER SENSE

The STBY pin, when active, prevents ac~s~$~ “the

MC146818A making it ideal for battery back-~’~~~l~ations.

DI

D2

Stand-by operation incorporates a transpa~~$$~~$tch, After

data strobe (DS) goes low (TD or .:>_.j$:r,n:<@),

recognized as a valid signal.

J$*$!3, N

STBY is

The STBY signal is totally asyR*L@6s.

Its transpare~t

latch is opened by the falling e~~.~$~,*,.%o2f’$\$.-@S (rising edge of RD

or ~R) and clocked by the r$@n@~dge of AS (ALE). There-

I

VDD

2.0 k

fore, for STBY to be reco$oize@t@S and AS should occur in

pairs. When STBY gop@~l,W,,before the falling edge of DS

Ps

(rising edge of ~R ?r ~~k$~re current cycle is completed at

that edge and thq \ $~h.<!.,.,.~.ycle will not be executsd.

S*, \“~*~>

PS – POW,~”:J~~$E, INPUT

The pQ,v&-s~$se pin is used in the control of the valid

RAM @~~~$ (VRT) bit in Register D. When the PS pin is

MC146818

+

Vss

0.005 ~F

I

low ~@q,w~~T bit is cleared to zero.

W~@’Using the VRT feature during powerup, the PS pin

T

must % externally held low for the specified tpLH time. As

power is applied, the VRT bit remains low indicating that the

contents of the RAM, time registers, and calendar are not

guaranteed. PS must go high after powerup to allow the

DI = M BD701 (Schottky) or Equivalent

D2 = 1N4148 or Equivalent

VRT bit to be set by a read of register D,

m MOTOROLA

Semiconductor Products Inc.

10

Share Link: