C5002 データシートの表示（PDF） - Cypress Semiconductor

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C5002

Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG

Cypress Semiconductor 

C5002

Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG

Approved Product

CAUTION: Switching clock frequencies without first disabling the clock may produce an output clock glitch

(short or stretched period clock) during frequency transition!)

2-Wire SMBus Control Interface

The 2-wire control interface implements write block mode write only slave interface. Sub addressing is not supported,

thus all preceding bytes must be sent in order to read or change one of the control bytes. The 2-wire control interface

allows each clock output to be individually controlled.

During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK

is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the

start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer

cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer

cycle is a 7-bit address with a Read/Write bit as the LSB (bit 0). Data is transferred MSB (bit 7) first.

The device will respond to writes up to 6 bytes (max) of data to address D0. The device will not respond to any other

control interface conditions.

Serial Control Registers

NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true

power up. Bytes are set to the values shown only on true power up.

Following the acknowledge of the Address Byte (D0), two additional bytes must be sent:

1) “Command Code “ byte, and

2) “Byte Count” byte.

Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.

After the Command Code and the Count bytes have been acknowledged, the described sequence below (Byte

0, Byte 1, Byte2,) will be valid and acknowledged.

Byte 0: Function Select Register (1 = enable, 0 = Stopped)

Bit

@Pup Pin# Description

7

1

14 CLK7 (Active = 1, Forced low = 0)

6

1

15 CLK6 (Active = 1, Forced low = 0)

5

1

18 CLK5 (Active = 1, Forced low = 0)

4

1

19 CLK4 (Active = 1, Forced low = 0)

3

1

22 CLK3 (Active = 1, Forced low = 0)

2

1

23 CLK2 (Active = 1, Forced low = 0)

1

1

26 CLK1 (Active = 1, Forced low = 0)

0

1

27 CLK0 (Active = 1, Forced low = 0)

Cypress Semiconductor Corporation

525 Los Coches St.

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

Document#: 38-07014 Rev. **

5/04/2001

Page 7 of 16

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