LV5256GP データシートの表示（PDF） - SANYO -> Panasonic
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LV5256GP Datasheet PDF : 9 Pages
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LV5256GP
Block Diagrams and Sample Application Circuit 1 (Step-down)
FB
V1
or
IN
V2
0.01µF at 1.25ms
OCP
0.1µF
REG_O
disable
100kΩ at 1MHz
RT
BIAS
disable
VREF
TSD
ot
Vref
VREG UVLO
OSC
3.3V
2.8V/2.5V
uvlo
Vref1R2
1.0V
(1.2V)
0.5V
(1.0V±1%)
disable
ot
uvlo
tout
+
pwm Control
+
+
+
Logic
+
du_sel
disable
uvlo
R
S
Q
tout
L/S
Vout-5
VREG
LDO with OPC
Vout-5
GND/ DU_SEL
OPEN
OPC_SEL
GND/OPEN: ×0.8
REG_O: ×0.4
L/S
×0.8
+
+
+
×0.4
+
Vref
+
du_sel
VrefR2
disable disable
uvlo
Vref1R2
TRAC_IN
SS
ONOFF
0.033µF at 3.3ms
vdd
pin heap 17 pin
VIN VIN=4.5 to 10V
1µF
VOUT
VOUT-5
0.022µF
V1 (Normal operation)
=1.0V to VIN
V2 (Tracking operaton)
=0V to VIN
22µH
SW
4.7µF
SBD
PGND
LGND
VDD
VDD=2.9 to 3.1V
0.1µF
Sample Application Circuit 2 (Step-up)
0.1µF
REG_O
disable
100kΩ at 1MHz
RT
FB
VOUT1
or
IN
VOUT2
0.01µF at 1.25ms
OCP
BIAS
disable
VREF
TSD
ot
Vref
VREG UVLO
OSC
3.3V
2.8V/2.5V
uvlo
Vref1R2
1.0V
(1.2V)
0.5V
(1.0V±1%)
disable
ot
uvlo
tout
+
pwm Control
+
+
+
Logic
+
du_sel
disable
uvlo
R
S
Q
tout
L/S
Vout-5
VREG
LDO with OPC
Vout-5
DU_SEL
REG_O
OPC_SEL
GND/OPEN: ×0.8
REG_O: ×0.4
L/S
×0.8
+
+
+
×0.4
+
Vref
+
du_sel
VrefR2
disable disable
uvlo
Vref1R2
TRAC_IN
SS
ONOFF
0.033µF at 3.3ms
vdd
pin heap 17 pin
VIN VIN=4.5~10V
1µF
VOUT
VOUT-5
VOUT1 (Normal operation)
=5.3V to 14V
VOUT2 (Tracking operaton)
=VIN or more
4.7µF
10µH
SW
PGND
LGND
VDD
VDD=2.9~3.1V
0.1µF
No.A1277-5/9
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