UPD78C12AL データシートの表示（PDF） - NEC => Renesas Technology
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UPD78C12AL Datasheet PDF : 66 Pages
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µPD78C10A,78C11A,78C12A
3. RESET OPERATIONS
When RESET Input becomes low, the system reset is activated to create the following status.
• INTERRUPT ENABLE F/F is reset and interrupt is disabled.
• All the interrupt mask registers are set (1) and interrupt is masked.
• An interrupt request flag is reset (0) and hold interrupt is eliminated.
• Each bit of PSW is reset (0).
• 0000H is loaded into the program counter (PC).
• The MODE A, MODE B, MODE C, and MODE F registers are set to FFH and the bits (MM0, 1, and 2) of the MODE
CONTROL C and MEMORY MAPPING registers are respectively reset (0), then all the
ports (A, B, C, D, and F) become input port (output high-impedance).
• All the test flags but SB flag are reset (0).
• A timer mode register is set to FFH, and TIMER F/F is reset.
• The mode register (ETMM, EOM) of a timer/event counter is reset (0).
• The serial mode high register(SMH) of serial interface is reset (0), while the serial mode low register (SML) is
set to 48H.
• The A/D channel mode register of the A/D converter is reset (0).
• WR, RD, ALE signals become high-impedance.
• The ZC1, ZC2 bits of the zero-cross mode register (ZCM) are set (1).
• The internal timing generator is initialized.
• Data memory and the following register contents are undefined:
Stack pointer (SP)
Expansion accumulator (EA, EA’), accumulator (A, A’)
General register (B, C, D, E, H, L, B’, C’, D’, E’, H’, L’)
Output latch of each port
TIMER REG0, 1 (TM0, TM1)
TIMER/EVENT COUNTER REG0, 1 (ETM0, ETM1)
RAE bit of MEMORY MAPPING register
SB flag of test flag
When RESET input becomes high, the reset status is released. Then, execution of the program is started from
0000H. The contents of various kinds of registers must be initialized or re-initialized in the program, if necessary.
Table 3-1 shows the state of each hardware after reset.
Table 3-2 shows the state of each pin after reset.
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