LTC2633AHTS8-HZ8 データシートの表示（PDF） - Linear Technology

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LTC2633AHTS8-HZ8

Dual 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference

Linear Technology 

LTC2633

Operation

Board Layout

The PC board should have separate areas for the analog and

digital sections of the circuit. A single, solid ground plane

should be used, with analog and digital signals carefully

routed over separate areas of the plane. This keeps digital

signals away from sensitive analog signals and minimizes

the interaction between digital ground currents and the

analog section of the ground plane. The resistance from

the LTC2633 GND pin to the ground plane should be as

low as possible. Resistance here will add directly to the

effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2633 is no more susceptible to

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

analog ground, digital ground, and power ground. When

the LTC2633 is sinking large currents, this current flows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

It is sometimes necessary to interrupt the ground plane

to confine digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

Package Description

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637 Rev A)

0.40

0.65

MAX

REF

2.90 BSC

(NOTE 4)

1.22 REF

3.85 MAX 2.62 REF

1.4 MIN

2.80 BSC

1.50 – 1.75

(NOTE 4)

PIN ONE ID

22

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.20 BSC

DATUM ‘A’

0.65 BSC

0.80 – 0.90

1.00 MAX

0.30 – 0.50 REF

0.09 – 0.20

NOTE:

(NOTE 3)

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

0.22 – 0.36

8 PLCS (NOTE 3)

0.01 – 0.10

1.95 BSC

TS8 TSOT-23 0710 REV A

2633fb

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